LO Divider Preset and Phase Alignment for Sleep-Wake Continuity
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Solution Overview
Problem
Maintaining local oscillator phase continuity in wireless communication devices is challenging, especially when PLL and LO circuitry is shut down or transitions between active and inactive states, due to ambiguity in phase and uncertainty of start-up timing, particularly in scenarios like sleep modes and multi-frequency operations.
Innovation Solution
The implementation of a local oscillator (LO) generator circuit that includes a PLL, frequency synthesizer, and LO divider circuit, utilizing a clock gating circuit, programmable divider, toggling accumulator, and decision logic to set a predetermined initial phase and align the VCO signal with a continuous phase signal, ensuring phase continuity upon start-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PLL and LO circuitry are shut down or placed in sleep mode to reduce power consumption, then energy efficiency is improved, but phase continuity is lost and start-up timing becomes uncertain
Solution Approach 1:
The patent applies preliminary action by presetting the LO divider to a predetermined initial phase state before the PLL is activated from sleep mode. This preliminary phase setting ensures that when the VCO starts oscillating, the LO signal already has the correct phase relationship, eliminating phase discontinuity without requiring continuous operation of the LO circuitry.
Solution Approach 2:
The patent implements feedback through a phase detection mechanism that monitors the phase relationship between the VCO signal and the LO signal. The decision logic circuit receives feedback about phase alignment status and controls the presetting of the LO divider to maintain continuous phase relationship, allowing the system to recover phase continuity after wake-up from sleep mode.
2Reliability
If the LO circuitry remains continuously active to maintain phase continuity, then phase coherence is preserved, but power consumption increases
Solution Approach 1:
The LO divider is preset to a predetermined initial phase before the PLL is activated, establishing the correct phase relationship in advance. This preliminary action eliminates the need for continuous LO operation to maintain phase coherence, as the phase relationship is established once during wake-up and maintained thereafter.
Solution Approach 2:
The system transitions from continuous operation to periodic operation by activating the LO circuitry only when needed (during wake-up from sleep mode) and using preliminary phase setting to maintain coherence. This periodic activation with preliminary preparation reduces power consumption while preserving phase continuity during active periods.
3Speed
If the PLL is quickly reactivated from sleep mode to maintain timing, then response speed is improved, but phase alignment becomes uncertain
Solution Approach 1:
The LO divider is preset to a predetermined initial phase state before the VCO is activated from sleep mode. This preliminary phase configuration allows the system to achieve both fast start-up and accurate phase alignment, as the phase relationship is established in advance rather than requiring slow convergence after activation.
Solution Approach 2:
The phase detection circuit provides feedback to verify that the preset phase relationship is correct after wake-up. This feedback mechanism ensures phase alignment accuracy while allowing rapid activation, as the system can quickly verify and adjust the phase relationship rather than requiring lengthy convergence periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the generation of an LO signal with continuous phase even when circuits are periodically powered on and off, conserving battery power while maintaining phase coherence, applicable to both receivers and transmitters in various wireless communication systems.
Implementation Method 1
a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit
Implementation Method 2
the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g)
Implementation Method 3
a local oscillator (LO) divider configured to receive the VCO output signal (vco_g)
Implementation Method 4
a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv
Implementation Method 5
a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal
Implementation Method 6
a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal
Data Source
AI summary
A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.