Local Oscillator Re-Clocking with Delay Alignment for Low Phase Noise
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Solution Overview
Problem
Conventional frequency divider circuits face challenges in achieving low phase noise and low power consumption over a wide tuning range, and re-clocking techniques struggle with metastability when the reference clock frequency is high, leading to instability in aligning the LO chain output signal.
Innovation Solution
A local oscillator signal generation circuit that includes a Programmable Delay Cell (PDL) and a control arrangement to align the rising edges of the data signal and reference clock signal using partially overlapping pulse windows, ensuring stable re-clocking by adjusting the phase relationship between the signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional VCO is used for frequency tuning, then frequency tuning capability is achieved, but phase noise performance deteriorates when tuning range is extended
Solution Approach 1:
The frequency division function is divided into multiple stages with different division ratios. The first frequency divider uses division ratio N1 for lower frequencies, while the second frequency divider uses division ratio N2 for higher frequencies. This segmentation allows the VCO to operate within a limited range with optimal phase noise, while achieving wide overall tuning range through the cascaded divider structure.
2Adaptability or versatility
If a programmable frequency divider is used to extend tuning range, then frequency range is improved, but device complexity increases
Solution Approach 1:
The frequency divider structure is made dynamic by allowing the division ratio to be programmably adjusted between different values (N1 and N2). This dynamic reconfiguration capability enables the system to adapt to different frequency ranges without requiring multiple fixed divider circuits, thereby extending tuning range while controlling complexity through a single reconfigurable unit.
3Use of energy by moving object
If re-clocking is performed at high reference clock frequencies, then power consumption is reduced, but metastability occurs causing signal instability
Solution Approach 1:
Before performing the re-clocking operation at high frequency, the system preliminarily adjusts the phase relationship between the reference clock signal and the LO chain output signal. By pre-aligning these signals to satisfy setup and hold time requirements, the system eliminates metastability conditions that would otherwise occur during high-frequency re-clocking, ensuring stable operation.
4Device complexity
If phase alignment is not properly controlled during re-clocking, then circuit simplicity is maintained, but metastability occurs leading to undefined output
Solution Approach 1:
The system implements feedback control to continuously monitor and adjust the phase relationship between the reference clock signal and the LO chain output signal. This feedback mechanism ensures that the phase alignment conditions for re-clocking are always satisfied, preventing metastability without requiring overly complex circuitry. The feedback loop dynamically compensates for phase drift and timing variations.
Data Source
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Figure 2A~2B
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AI summary
A local oscillator signal generation circuit is presented. The circuit comprises: a delay device adapted to delay a data signal according to a control signal; a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided to its clock input terminal; and a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and to generate a control signal based on the first and second partially overlapping pulse windows and the reference clocking signal. The control signal is provided to the delay device to control the amount by which the data signal is delayed so as to align the rising edges of the data signal and the reference clock signal. A local oscillator signal is derived from the output of the data flip-flop.