Load Acquire Store Release Instructions Using Data Memory Barriers
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Solution Overview
Problem
In reduced instruction set computing (RISC) environments, the complex acquire and release semantics for memory operation ordering can be cumbersome, requiring intricate combinations of instructions to ensure correct memory operation sequencing.
Innovation Solution
The introduction of data memory barriers simplifies memory operation ordering by enforcing constraints on memory operations before and after the barriers, allowing for straightforward ordering using load with acquire and store with release instructions, which consist of a load or store operation followed by a data memory barrier, ensuring proper sequencing without the need for complex combinations of instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex combinations of store release and load acquire instructions are used to ensure correct memory operation sequencing, then memory operation ordering reliability is improved, but instruction complexity and ease of operation deteriorate
Solution Approach 1:
The patent segments memory operation ordering into distinct phases using memory barriers. Full barriers divide memory operations into before-barrier and after-barrier groups, ensuring all operations in one group complete before operations in the other group begin. This segmentation simplifies the complex ordering requirements by breaking them into manageable, enforceable segments.
Solution Approach 2:
The patent introduces memory barriers as intermediary instructions between load/store operations and subsequent memory operations. These barrier instructions act as mediators that enforce ordering constraints without requiring complex combinations of acquire/release semantics. The barrier serves as an intermediate control point that simplifies the ordering protocol.
2Reliability
If data memory barriers are used with load and store operations to enforce ordering, then memory operation sequencing reliability is improved, but instruction complexity is reduced
Solution Approach 1:
The patent merges the functionality of acquire/release semantics with standard load/store operations by appending memory barrier instructions. Instead of requiring separate complex acquire/release instruction combinations, the solution combines ordering enforcement with basic memory operations, creating simpler composite instructions that achieve the same reliability.
Solution Approach 2:
The patent changes the ordering parameters of memory operations by introducing barrier-type instructions with different ordering strengths. Full barriers enforce complete ordering of all memory operations, while lightweight barriers provide partial ordering. This parameter-based approach allows flexible control of memory ordering without increasing overall system complexity.
Data Source
AI summary
A system and method are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low-level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier ensures that prior instructions are performed and completed before subsequent instructions are executed.