Load-Aware ECMP Central State Machine for Congestion Avoidance

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Solution Overview

Problem

Existing equal-cost multipath (ECMP) routing strategies are limited by fixed path selection based on flow-hash, lack of instantaneous congestion awareness, and slow response times, leading to network congestion and packet reordering issues.

Innovation Solution

The implementation of a load-aware ECMP system using a central state machine that dynamically balances traffic by considering instantaneous loading and congestion across networks, reducing the need for local packet-level path selection and enabling faster, more accurate path choices through centralized management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard ECMP with flow-hash is used for path selection, then path selection is simple and fixed, but network congestion cannot be detected and packet reordering occurs

Engineering Contradiction:
Improvecongestion awarenessVSAvoidpath selection mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where network devices continuously monitor congestion states and path utilization metrics, then use this feedback information to dynamically adjust ECMP path selection. This allows the system to detect congestion and respond appropriately, resolving the contradiction between simple fixed path selection and congestion awareness.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent transforms static ECMP path selection into a dynamic system that adapts to changing network conditions. By introducing mechanisms to detect instantaneous loading and congestion, the system can dynamically reroute traffic away from congested paths while maintaining load balancing, thus achieving both reliability and adaptability.

Inventive Principle:
Principle #15Dynamics

2Speed

If software-based flow let-switching is used to manipulate packet-header fields, then path manipulation is possible, but response time is severe and packet reordering occurs

Engineering Contradiction:
Improveresponse timeVSAvoidpacket ordering
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent pre-computes and caches alternative paths and routing decisions before congestion occurs. When congestion is detected, the system can immediately switch to pre-prepared alternative routes without requiring complex real-time calculations, thus achieving fast response time while maintaining packet ordering through coordinated switching.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary mechanisms such as path computation elements and routing controllers that mediate between congestion detection and path selection. These intermediaries handle the complex path manipulation logic, enabling fast response times while ensuring proper packet ordering through coordinated control, thus resolving the contradiction between speed and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If fixed ECMP paths are programmed by software, then desired paths can be specified, but response time is limited and reconfiguration is slow

Engineering Contradiction:
Improvepath configuration flexibilityVSAvoidreconfiguration time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements dynamic path configuration that combines software-programmable desired paths with real-time adaptation capabilities. The system maintains flexibility to specify desired paths through software while incorporating mechanisms to dynamically adjust routing decisions based on current network conditions, thus achieving both adaptability and fast response without requiring complete reconfiguration.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4075756B1Load-aware ECMP with flow tables
Publication Date: 2024.05.22 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of ports and several pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can determine at least one feature of the overlay network and a corresponding group of paths within the underlay network.