Load Board BIST for SIP System-Level Testing
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Solution Overview
Problem
Conventional methods for testing System-in-Package (SIP) devices using Automatic Test Equipment (ATE) are inefficient and fail to effectively verify system-level connectivity and functionality, as they are adapted from testing integrated circuits, which do not account for the complex interconnections and multiple components within SIPs.
Innovation Solution
Implementing a Built-in Self Test (BIST) capability within the SIP, where the ATE interacts with a test controller using state machines and control signals to conduct tests, allowing for the execution of functional representations of tests stored in memory, and verifying the load board and external connections before proceeding with testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional ATE methods adapted from integrated circuit testing are used for SIP devices, then the testing process is simplified and uses existing equipment, but system-level connectivity and functionality cannot be effectively verified
Solution Approach 1:
The patent introduces a load board as an intermediary component between the ATE and the SIP device. The load board provides system-level interconnection and control capabilities that enable verification of system-level connectivity and functionality while using existing ATE equipment. The load board acts as a mediator that bridges the gap between component-level testing capabilities and system-level testing requirements.
2Measurement precision
If individual components in a SIP are tested separately using multiple testers, then each component can be thoroughly tested, but the testing process becomes time-consuming and redundant
Solution Approach 1:
The patent merges multiple component testing functions into a single integrated load board that can test all components within a SIP device simultaneously. Instead of using multiple separate testers for different components, the load board provides a unified testing platform that maintains thorough component-level testing while significantly improving testing throughput by eliminating redundant testing operations.
3Quantity of substance
If all components and devices in a SIP are pinned out for individual testing, then complete component coverage is achieved, but the package pins are insufficient due to multiple interconnections
Solution Approach 1:
The patent transitions from a two-dimensional pin-out approach to a three-dimensional testing architecture by introducing the load board as an intermediate layer. The load board provides additional connection points and routing pathways that are not constrained by the limited package pins of the SIP device. This dimensional expansion allows complete coverage of all components within the SIP without requiring additional package pins.
4Reliability
If memory is tested using a SIP's processor, then the processor-memory interface is verified, but the test time becomes very long and cost prohibitive
Solution Approach 1:
The patent performs preliminary testing of the memory and processor-memory interface using the load board before the actual SIP device is tested. The load board can independently verify memory functionality and interface connectivity in advance, eliminating the need for time-consuming memory tests during processor operation. This preliminary action ensures the processor-memory interface is verified while significantly reducing overall test time.
Data Source
AI summary
Systems, methods, and computer program products directed to testing a System-in-a-Package (SIP) using an Automatic Test Equipment (ATE) machine. A functional representation of one or more tests to be performed in the SIP is loaded in a memory located on a load board, the load board located on the ATE machine. A test controller located on at least one of the SIP and the load board is caused to retrieve and store the one or more tests to be performed in the SIP. The test controller is instructed to conduct the one or more tests in the SIP.