Load Driving Circuit With Bias Boost for Fast Output Rise
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Solution Overview
Problem
In load driving circuits for switching power supplies and inverters, the large parasitic capacitance of NPN transistors increases the time it takes for the output voltage to reach the high logic level, leading to increased consumption current when trying to reduce rise time.
Innovation Solution
A load driving circuit with a bias current circuit, control circuit, and driving circuit that adjusts the current value and control signal levels to rapidly change the output voltage in response to input signal logic levels, using current mirrors and capacitors to manage the charging and discharging of currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the NPN transistor Q130 is designed greater in size to heighten current driving capacity, then the current driving capacity is improved, but the parasitic capacity increases and the rise time of output voltage increases
Solution Approach 1:
The patent applies preliminary action by pre-charging a capacitor (C1) to a voltage higher than the power supply voltage before the switching operation. When the NPN transistor Q100 switches, this pre-charged capacitor provides an immediate voltage boost to the base of the output transistor Q130, enabling rapid turn-on without requiring the transistor to be oversized. This resolves the contradiction by achieving fast rise time through advance preparation rather than increasing transistor size.
Solution Approach 2:
The patent changes the voltage parameter of the capacitor from the normal power supply voltage to a higher voltage level through pre-charging. This parameter change allows the capacitor to deliver a stronger voltage boost signal to the transistor base, achieving faster switching speed without increasing the transistor's physical size, thus resolving the trade-off between current driving capacity and rise time.
2Loss of time
If the current I1 of the current source 210 is increased to reduce rise time of output voltage, then the rise time is reduced, but the consumption current of the load driving circuit increases
Solution Approach 1:
The patent employs periodic action by charging the capacitor C1 only during the period when the input signal is at low level (non-switching period), and then utilizing this stored energy during the switching period when high-speed turn-on is needed. This periodic charging and discharging cycle allows the circuit to achieve fast rise time only when necessary, rather than maintaining high current continuously, thus reducing overall consumption current while still achieving rapid voltage transition when required.
3Power
If the NPN transistor Q130 is designed greater in size to heighten current driving capacity, then the current driving capacity is improved, but the parasitic capacity increases leading to longer switching time
Solution Approach 1:
The patent applies preliminary action by pre-charging a capacitor (C1) to a voltage higher than the power supply voltage before the switching operation. When the NPN transistor Q100 switches, this pre-charged capacitor provides an immediate voltage boost to the base of the output transistor Q130, enabling rapid turn-on without requiring the transistor to be oversized. This resolves the contradiction by achieving fast rise time through advance preparation rather than increasing transistor size.
Solution Approach 2:
The patent changes the voltage parameter of the capacitor from the normal power supply voltage to a higher voltage level through pre-charging. This parameter change allows the capacitor to deliver a stronger voltage boost signal to the transistor base, achieving faster switching speed without increasing the transistor's physical size, thus resolving the trade-off between current driving capacity and rise time.
Data Source
AI summary
A load driving circuit comprising: a bias current circuit configured to generate a bias current having a current value corresponding to a level of a control signal; a control circuit configured to control the level of the control signal so that the bias current is increased and thereafter decreased, when an input signal reaches one logic level; and a driving circuit configured to raise an output voltage for driving a load to a higher logic level in a time corresponding to the current value of the bias current, when the input signal reaches the one logic level, and lower the output voltage to a lower logic level, when the input signal reaches the other logic level.