Out-of-order processor load fault resolution via instant reclamation
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Solution Overview
Problem
In computer processor architectures, load faults in out-of-order execution are typically resolved at retirement, which nullifies the benefits of out-of-order execution as all preceding instructions have already executed, whereas instant reclamation for mis-predicted branches allows faults to be detected and resolved during execution, not providing this capability for load instructions.
Innovation Solution
The implementation of an instant reclamation system that detects and resolves load faults as soon as they occur, allowing faulty load instructions to be re-fetched and re-executed out-of-order, similar to mis-predicted branches, by utilizing a memory ordering buffer, reservation station, and load information table to generate an early instant reclamation request and reconstruct the load address based on preceding branch instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load faults are resolved at retirement of the load instruction, then the fault resolution is simple and follows the traditional retirement process, but the benefits of out-of-order execution are nullified since all preceding instructions have already executed and the load instruction is now being executed in program order
Solution Approach 1:
The patent applies preliminary action by detecting load faults during the execution phase (before retirement) and immediately initiating re-fetching and re-execution. The memory ordering buffer monitors load instructions and detects faults as they occur, triggering instant reclamation before the instruction reaches retirement. This allows the processor to correct faults while maintaining out-of-order execution benefits, rather than waiting until retirement when all preceding instructions have already executed.
2Loss of time
If instant reclamation is implemented for load instructions, then faster fault resolution is achieved by detecting and re-fetching faults during execution, but the device complexity increases compared to traditional retirement-based resolution
Solution Approach 1:
The patent applies universality by extending the instant reclamation mechanism, originally designed for mis-predicted branches, to also handle load instruction faults. The memory ordering buffer and associated structures are enhanced to serve dual purposes: monitoring both branch predictions and load instructions for faults. This multi-functional approach allows the same infrastructure to handle different types of faults, reducing the need for separate dedicated systems and mitigating the complexity increase.
Solution Approach 2:
The patent introduces the memory ordering buffer as an intermediary component that mediates between the execution units and the fault resolution mechanism. This buffer monitors load instructions, detects faults, and triggers re-fetching operations. By placing this intermediary layer, the system can detect and resolve faults during execution without requiring complex direct integration between all execution units and the fault handling logic, thus managing complexity while enabling fast fault resolution.
3Use of energy by moving object
If load faults are detected and resolved at retirement, then the fault detection mechanism is simple and relies on existing retirement infrastructure, but power consumption increases due to the need to re-execute instructions after retirement
Solution Approach 1:
The patent applies preliminary action by detecting load faults during the execution phase (before retirement) and immediately initiating re-fetching and re-execution. The memory ordering buffer monitors load instructions and detects faults as they occur, triggering instant reclamation before the instruction reaches retirement. This allows the processor to correct faults while maintaining out-of-order execution benefits, rather than waiting until retirement when all preceding instructions have already executed.
Data Source
AI summary
A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.