Load-Free AND Gate Clock Divider for Low-Power Fast Switching
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Solution Overview
Problem
Existing AND gates and clock divider circuits consume high power and have slow switching speeds, particularly in applications with low power budgets, such as those using NFC antennas.
Innovation Solution
The design incorporates field effect transistors (FETs) and diodes to create load-free AND gates and clock divider stages, reducing power consumption and increasing switching speed by eliminating load resistors and utilizing diode-connected configurations to generate clock signals from low power inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional AND gate configurations with load resistors are used, then the circuit can provide proper logic levels, but the power consumption increases and switching speed decreases
Solution Approach 1:
The patent removes the load resistor from the conventional AND gate configuration, extracting the component that causes power consumption and speed limitations. The load-free unipolar AND gate achieves proper logic levels without requiring a load resistor, thereby reducing power consumption and improving switching speed.
Solution Approach 2:
The patent changes the operational parameters of the AND gate by using unipolar logic (single polarity voltage levels) instead of bipolar logic. This parameter change eliminates the need for load resistors and enables operation with lower power consumption and faster switching speeds while maintaining proper logic level generation.
2Reliability
If load resistors are included in AND gate configuration, then proper logic levels can be maintained, but the switching speed becomes slower
Solution Approach 1:
The load resistor is extracted from the circuit configuration. The unipolar AND gate maintains reliable logic levels through its transistor configuration and voltage relationships without requiring a load resistor, achieving both speed improvement and logic level stability.
Solution Approach 2:
The patent replaces the mechanical/resistive load-based logic level generation with a field-effect transistor-based voltage control mechanism. The FETs inherently provide proper logic levels through their voltage-controlled conductivity, substituting the need for load resistors and enabling faster switching.
3Productivity
If conventional clock divider circuits are used, then frequency division can be achieved, but power consumption is high
Solution Approach 1:
The patent removes load resistors from the clock divider circuit configuration, extracting the power-consuming component. The load-free unipolar AND gates maintain frequency division functionality while significantly reducing power consumption, making the circuit suitable for low-power applications.
Solution Approach 2:
The clock divider circuit operates using unipolar logic parameters throughout, changing from conventional bipolar logic. This parameter change propagates through the entire circuit, reducing power consumption at each stage while maintaining the frequency division capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in AND gates and clock divider stages that operate faster and consume less power, enabling efficient clock division even with very low power budgets, such as in NFC applications, by reducing the number of loads and leveraging diode-connected configurations for efficient signal processing.
Implementation Method 1
a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal
Implementation Method 2
first and second diodes, each having a respective first terminal and a respective second terminal, and having a forward conduction direction from the respective second terminal to the respective first terminal
Data Source
AI summary
An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.