Load-Mark Metadata for Cache Line Invalidation Control
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Solution Overview
Problem
In multiprocessor systems, load-marked cache lines are often invalidated unnecessarily, leading to performance issues due to interfering accesses and the need for threads to re-request cache lines, which hampers the performance of threads that have placed or will place load-marks on these lines.
Innovation Solution
A system that maintains load-marks on cache lines by using a modified cache-coherency protocol to provide a negative response to requests that would invalidate a load-marked cache line, thereby retaining the cache line and its load-mark in the metadata and preventing unnecessary invalidations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system invalidates load-marked cache lines to maintain cache coherence, then cache coherence is maintained, but thread performance deteriorates due to unnecessary invalidations and re-requests
Solution Approach 1:
The patent applies local quality by differentiating the treatment of cache lines based on their load-mark status. Load-marked cache lines receive special protection from invalidation, while non-load-marked lines follow standard invalidation procedures. This localized differentiation allows the system to maintain cache coherence for unprotected lines while preserving thread performance for protected lines, resolving the contradiction between coherence reliability and thread productivity.
Solution Approach 2:
The load-mark metadata acts as an intermediary mechanism between the cache coherence protocol and the cache line data. This intermediary layer allows the system to selectively control invalidation behavior based on the presence of load-marks, enabling threads to maintain access to frequently read cache lines while still allowing invalidation of lines that don't have active load-marks, thus balancing coherence requirements with performance optimization.
2Productivity
If the system allows multiple threads to load-mark the same cache line simultaneously, then read throughput increases, but cache control complexity increases
Solution Approach 1:
The patent segments the cache line metadata into distinct fields, including a load-mark indicator and a reader count. This segmentation allows the cache control system to track multiple readers independently using a simple counter mechanism rather than complex inter-thread coordination. Each thread can increment the reader count atomically, enabling multiple simultaneous load-marks with minimal control logic, thus increasing read throughput without significantly increasing cache control complexity.
Solution Approach 2:
The system uses a copied counter approach where each cache line has an associated reader count copy in its metadata. This copied counter serves as a simple, scalable mechanism to track multiple load-marking threads without requiring complex shared state management. The counter can be incremented and decremented independently for each cache line, allowing multiple threads to load-mark simultaneously while keeping the control mechanism simple and efficient.
Data Source
AI summary
Embodiments of the present invention provide a system that maintains load-marks on cache lines. The system includes: (1) a cache which accommodates a set of cache lines, wherein each cache line includes metadata for load-marking the cache line, and (2) a local cache controller for the cache. Upon determining that a remote cache controller has made a request for a cache line that would cause the local cache controller to invalidate a copy of the cache line in the cache, the local cache controller determines if there is a load-mark in the metadata for the copy of the cache line. If not, the local cache controller invalidates the copy of the cache line. Otherwise, the local cache controller signals a denial of the invalidation of the cache line and retains the copy of the cache line and the load-mark in the metadata for the copy of the cache line.