Load Miss Result Buffer for Out-of-Order Data Hazard Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Load store units face data hazards when missed load instructions are reissued out of order, complicating the tracking system and requiring extensive resources to manage potential data inaccuracies.
Innovation Solution
A load/store unit configuration with an outstanding load miss buffer and a load miss result buffer allows missed load instructions to be reissued without data hazards by storing and retrieving data from the load miss result buffer instead of the level one data cache, eliminating the need for complex tracking systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If missed load instructions are reissued out of order to improve performance, then productivity is improved, but data hazards occur and device complexity increases
Solution Approach 1:
The patent introduces an intermediary buffer structure (outstanding load miss buffer with primary and dependent entries) that mediates between the out-of-order execution engine and the in-order data dependency requirements. This buffer tracks which load instructions are outstanding and ensures proper data delivery order without requiring complex external tracking systems.
Solution Approach 2:
The patent creates a copy of the load instruction metadata in the outstanding load miss buffer, including dependency information. This copying approach allows the system to track data hazards without modifying the original instruction stream or requiring complex real-time analysis of all outstanding instructions.
2Reliability
If a complex tracking system is implemented to manage data hazards, then reliability is improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent performs preliminary action by pre-establishing the buffer structure with primary and dependent entries before data hazards can occur. The dependency relationships are captured in advance when instructions are dispatched, eliminating the need for complex real-time tracking and resolution mechanisms.
Solution Approach 2:
The patent changes the parameter of data storage organization by using a hierarchical buffer structure with primary entries for independent loads and dependent entries for loads with data dependencies. This parameter change simplifies the tracking logic by organizing data according to its dependency characteristics rather than requiring general-purpose complex tracking.
3Speed
If data is retrieved from level one cache for reissued load instructions, then speed is improved, but data hazards occur due to out of order reissuance
Solution Approach 1:
The outstanding load miss buffer acts as an intermediary between the fast level one cache and the load instruction execution stream. It allows rapid data retrieval from the cache while simultaneously managing the ordering and dependency requirements, ensuring that data is delivered to instructions in the correct order even though retrieval occurs at high speed.
Solution Approach 2:
The system performs preliminary action by pre-loading data into the buffer structure and pre-establishing dependency relationships before reissued load instructions need their data. This allows the cache to operate at full speed without waiting for complex dependency resolution, as the buffering structure is already in place to handle the ordering requirements.
Data Source
AI summary
A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits, shared data lines and shared data selection circuits. The dependent data selection circuits are configured to select a subset of data from the memory system for storing in an associated dependent data line. Similarly, the shared data selection circuits are configured to select a subset of data from the memory system for storing in an associated shared data line.