Load Queue Address Proxies for Store-to-Load Forwarding Checks
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Solution Overview
Problem
Cache memories in microprocessors significantly impact performance due to access time and cache coherency issues, which are exacerbated by the need to reduce cache memory access time and improve hit rates while maintaining efficient cache capacity and size, particularly in multi-processor systems.
Innovation Solution
Implementing a microprocessor with a load/store unit that performs store-to-load forwarding using a physically-indexed, physically-tagged second-level set-associative cache, store and load queues, and address proxies (PAPs) to manage cache coherency and reduce unnecessary cache information, enabling efficient store-to-load forwarding checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memory capacity is increased to improve hit rates, then processor performance improves, but cache access time increases and device complexity increases
Solution Approach 1:
The cache memory is divided into multiple cache sets, each containing multiple cache ways. This segmentation allows the cache to be organized into manageable units that can be accessed in parallel, improving both hit rate and access time simultaneously by distributing data across multiple smaller, faster-accessible units.
Solution Approach 2:
The patent introduces a new dimension to cache organization by implementing set-associative structure with multiple ways per set. This multi-dimensional organization (sets × ways) allows the cache to achieve higher hit rates through increased capacity while maintaining fast access times through parallel way selection within each set.
2Reliability
If cache memory capacity is increased to improve hit rates, then processor performance improves, but device complexity and physical size increase
Solution Approach 1:
By segmenting the cache into standardizable sets and ways, the design complexity is managed through modular repetition. Each set-way unit follows the same structure, allowing complex large-capacity caches to be built from simpler, replicated building blocks rather than custom designs.
Solution Approach 2:
The cache set and way structures are designed as universal, reusable units that can be replicated to create caches of various sizes. This universality reduces design complexity by using the same structural templates across different cache configurations, minimizing the need for unique design elements.
3Productivity
If store-to-load forwarding is implemented to reduce cache access time, then instruction execution rate improves, but device complexity increases due to additional queue structures and address comparison logic
Solution Approach 1:
The patent creates simplified copies of address information (address proxies) in the store and load queues instead of storing complete address details. These proxies contain only the essential set index and way information needed for forwarding decisions, reducing the complexity of address comparison logic while enabling fast store-to-load forwarding.
Solution Approach 2:
Address proxies are pre-computed and stored in the queues when store and load instructions are initially queued, rather than computing full address comparisons at execution time. This preliminary preparation of address information simplifies the forwarding decision process and reduces the complexity of real-time comparison logic.
4Reliability
If physical address proxies are stored in load queue entries to enable correctness checks, then cache coherency is improved, but device complexity and power consumption increase
Solution Approach 1:
Instead of storing complete physical addresses in load queue entries, the patent stores simplified address proxies containing only the necessary set index and way information. This copying of essential address elements enables coherency checks while significantly reducing the power consumption associated with storing and comparing large address values.
Solution Approach 2:
The patent extracts only the critical components of the physical address (set index and way information) needed for coherency checking, removing unnecessary address bits. This extraction reduces the amount of data that must be stored and processed, thereby lowering power consumption while maintaining coherency guarantees.
Data Source
AI summary
A microprocessor includes a load/store unit that performs store-to-load forwarding, a PIPT L2 set-associative cache, a store queue having store entries, and a load queue having load entries. Each L2 entry is uniquely identified by a set index and a way. Each store/load entry holds, for an associated store/load instruction, a store/load physical address proxy (PAP) for a store/load physical memory line address (PMLA). The store/load PAP specifies the set index and the way of the L2 entry into which a cache line specified by the store/load PMLA is allocated. Each load entry also holds associated load instruction store-to-load forwarding information. The load/store unit compares the store PAP with the load PAP of each valid load entry whose associated load instruction is younger in program order than the store instruction and uses the comparison and associated forwarding information to check store-to-load forwarding correctness with respect to each younger load instruction.