Load Queue Byte-Level Data Accumulation for Cache Latency Reduction

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Solution Overview

Problem

Conventional processors experience unsatisfactory latency due to cache misses, where they need to wait for data to be fetched from the next cache level or main memory, impacting performance.

Innovation Solution

A method that uses a load queue to temporarily store data portions from hierarchical cache sources, allowing data to be collected one or more bytes at a time from each source, enabling the load operation to execute without waiting for the entire cache line to be fetched from main memory or the next level cache.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor waits for the entire cache line to be fetched from main memory or next level cache, then data consistency is ensured, but latency increases and processor performance deteriorates

Engineering Contradiction:
Improvedata consistencyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The cache line fetch operation is segmented into individual byte transfers. The load queue stores data byte-by-byte as it becomes available from different cache levels, rather than requiring the entire cache line to be fetched before processing can continue. This segmentation allows the processor to complete loads using available bytes while the remaining bytes are still being transferred.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The load queue pre-allocates storage locations for load data before the entire cache line is fetched. By preparing the destination buffer in advance and filling it incrementally as data arrives from various cache levels, the system enables early load completion without waiting for the full cache line transfer to finish.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the processor uses a load queue to store data byte-by-byte from hierarchical cache sources, then latency is reduced and processor performance improves, but device complexity increases

Engineering Contradiction:
Improveprocessor performanceVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The load queue serves multiple functions: it acts as a temporary storage buffer for byte-by-byte data arrival, manages data from multiple hierarchical cache sources simultaneously, tracks which bytes have been received, and enables early load completion. This multi-functionality reduces the need for separate specialized structures for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The load queue acts as an intermediary structure between the cache hierarchy and the execution units. It mediates the data flow by buffering bytes as they arrive from different cache levels and making them available to the processor in the correct order, simplifying the interface between the complex cache hierarchy and the execution pipeline.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If the processor fetches the entire cache line from main memory or next level cache, then all data is available for future operations, but time is lost during the fetch operation

Engineering Contradiction:
Improvedata availabilityVSAvoidfetch time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The processor performs partial action by completing load operations with the bytes that are available, rather than waiting for the excessive action of fetching the entire cache line. The load queue accumulates bytes as they arrive, and once sufficient bytes are present to satisfy the load request, the operation completes immediately, even if the full cache line has not yet been fetched.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10552334B2Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early
Publication Date: 2020.02.04 INTEL CORP
  • US10552334B2 patent drawing
  • US10552334B2 patent drawing
  • US10552334B2 patent drawing

AI summary

A method and system acquires cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method and system, a store queue is accessed for one or more portions of a cache line associated with the load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load.