Non-Coherent Processor Load Queue Coherence Handling
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Solution Overview
Problem
In integrated circuits, maintaining cache coherence across both cacheable and uncacheable memory regions is challenging, particularly in multiprocessor systems, leading to issues with stale data and ordering violations, which increases software complexity and reduces system performance.
Innovation Solution
A non-coherent processor with a load queue that maintains status information for load instructions, using indicators to conditionally flush and replay instructions, and employing a weakly ordered memory consistency model to handle cacheable and non-cacheable loads, ensuring coherence across the memory system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order execution is implemented to increase instruction throughput, then productivity is improved, but maintaining memory coherence and ordering becomes more difficult
Solution Approach 1:
A load queue is introduced as an intermediary structure between the out-of-order execution engine and the memory system. The load queue tracks pending load instructions, their addresses, and timing information, enabling the processor to speculate on load outcomes while maintaining the ability to detect and correct ordering violations with respect to store instructions.
Solution Approach 2:
Load instructions are speculatively executed and their results preliminary committed to the load queue before actual memory access completion. This preliminary action allows the processor to continue execution without waiting for memory operations, while still maintaining the ability to enforce ordering constraints when stores are encountered.
2Productivity
If speculative execution of load instructions is performed, then productivity is improved, but stale data issues and ordering violations increase
Solution Approach 1:
The load queue provides feedback mechanisms that track the status of speculative load instructions. When a store instruction is executed, the system checks the load queue for any pending loads to the same address that occurred earlier in program order. If such loads exist, the store triggers a replay of the load to ensure correct ordering, thus providing feedback that maintains reliability while allowing speculative execution to proceed.
Solution Approach 2:
The system prepares for potential ordering violations by maintaining detailed records in the load queue before violations actually occur. This cushioning approach stores address information and timing data for all pending loads, enabling the system to detect and correct ordering issues with stores without compromising the benefits of speculative execution.
3Adaptability or versatility
If non-coherent domain access is allowed for flexibility, then adaptability is improved, but software complexity increases to maintain coherency
Solution Approach 1:
The processor implements self-service mechanisms for maintaining coherence with non-coherent devices. The load queue automatically tracks loads to addresses that may be accessed by non-coherent devices, and the coherence logic autonomously detects ordering violations and triggers replays when necessary. This self-service approach eliminates the need for complex software protocols while maintaining memory coherence.
Data Source
AI summary
Systems, apparatuses, and methods for processing load instructions are disclosed. A processor includes at least a data cache and a load queue for storing load instructions. The load queue includes poison indicators for load instructions waiting to reach non-speculative status. When a non-cacheable load instruction is speculatively executed, then the poison bit is automatically set for the load instruction. If a cacheable load instruction is speculatively executed, then the processor waits until detecting a first condition before setting the poison bit for the load instruction. The first condition may be detecting a cache line with data for the load instruction being evicted from the cache. If an ordering event occurs for a load instruction with a set poison bit, then the load instruction may be flushed and replayed. An ordering event may be a data barrier or a hazard on an older load targeting the same address as the load.