Load Queue Snoop Hit Detection for Out-of-Order Memory Ordering
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Solution Overview
Problem
Processors face challenges in maintaining strong memory ordering rules when loads are performed out of program order, potentially leading to violations due to incorrect data transfer sequences between processors.
Innovation Solution
A processor with a load/store unit (LSU) that includes a queue to track data cache hit status for each load, allowing for accurate detection of snoop hits and resynchronization to maintain correct memory ordering by updating cache hit status and using a snoop index to determine snoop hits without full address comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If loads are performed out of program order to improve performance, then processing speed is improved, but strong memory ordering rules may be violated
Solution Approach 1:
The patent applies preliminary action by tracking cache hit status for each load in the load queue before the loads are retired. The control unit updates the data cache hit status of each load represented in the queue as cache content changes, and detects snoop hits on loads before they complete. This advance tracking and detection mechanism ensures that even though loads execute out of order, their ordering relationships are properly maintained and detected, allowing the system to achieve both out-of-order execution performance and memory ordering correctness.
2Measurement precision
If full address comparison is used to detect snoop hits, then detection accuracy is improved, but processing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the address comparison task into two parts: the load/store unit maintains a load queue with cached index information for each load, and the data cache maintains its own index structure. When a snoop operation occurs, only the index portions need to be compared rather than full addresses. This segmentation of the comparison task reduces the complexity of snoop hit detection while maintaining accurate detection, as the index comparison is sufficient to identify potential snoop hits on loads in the queue.
Data Source
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AI summary
In one embodiment, a processor (10) comprises a data cache (16) and a load/store unit (LSU) (20). The LSU (20) comprises a queue (24) and a control unit (26), and each entry in the queue (24) is assigned to a different load that has accessed the data cache (16) but has not retired. The control unit (26) is configured to update the data cache hit status of each load represented in the queue (24) as a content of the data cache (16) changes. The control unit (26) is configured to detect a snoop hit on a first load in a first entry of the queue (24) responsive to: the snoop index matching a load index stored in the first entry, the data cache hit status of the first load indicating hit, the data cache (16) detecting a snoop hit for the snoop operation, and a load way stored in the first entry matching a first way of the data cache (16) in which the snoop operation is a hit.