Load Queue Wrap Value Mediates Store Conflicts

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Solution Overview

Problem

In weakly-ordered memory models, modern out-of-order processors face challenges in efficiently completing load and store instructions, particularly in ensuring that younger loads do not conflict with older stores, which can lead to processing bottlenecks and inefficiencies.

Innovation Solution

The processor employs a load queue and a store queue with associated queue information, using wrap values to determine the relative ages of instructions and allow younger loads to be retired ahead of older stores without memory-address dependencies, thereby enabling flexible load and store retirement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If younger loads are permitted to access memory and complete ahead of older stores, then processing efficiency is improved, but memory consistency and ordering guarantees may be violated

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidmemory consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a mediation mechanism that uses queue information (load queue index, store queue index, wrap value) to mediate between younger loads and older stores. The completion logic acts as an intermediary that selectively allows loads to complete ahead of stores only when dependency checks confirm no memory-address conflicts exist, thus maintaining memory consistency while enabling out-of-order completion for efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If loads and stores are held in queues until criteria are met, then memory consistency is maintained, but processing speed is reduced

Engineering Contradiction:
Improvememory consistencyVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements dynamic queue management where the completion order of loads and stores is not fixed but adapts based on runtime conditions. The system dynamically determines whether to complete loads ahead of stores by checking dependency criteria (memory-address dependencies) at completion time, allowing the processor to switch between in-order and out-of-order completion based on actual memory access patterns and dependency states.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of completion timing from a static rule-based system to a dynamic parameter-driven system. By using queue indices and wrap values as parameters, the system can flexibly adjust completion order based on the specific state of the load and store queues, enabling faster completion when parameters indicate no conflicts exist.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If wrap values are used to track load and store positions, then flexibility in retirement is improved, but queue management complexity increases

Engineering Contradiction:
Improveflexibility in retirementVSAvoidqueue management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent adds a temporal dimension to queue management by introducing wrap values that track how many times the queue has been traversed. This additional dimension (wrap count) allows the system to distinguish between loads/stores that are genuinely older versus those that appear older due to queue wraparound, enabling flexible retirement decisions without complex comparison logic.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9535695B2Completing load and store instructions in a weakly-ordered memory model
Publication Date: 2017.01.03 APPLE INC
  • US9535695B2 patent drawing
  • US9535695B2 patent drawing
  • US9535695B2 patent drawing

AI summary

Techniques are disclosed relating to completion of load and store instructions in a weakly-ordered memory model. In one embodiment, a processor includes a load queue and a store queue and is configured to associate queue information with a load instruction in an instruction stream. In this embodiment, the queue information indicates a location of the load instruction in the load queue and one or more locations in the store queue that are associated with one or more store instructions that are older than the load instruction. The processor may determine, using the queue information, that the load instruction does not conflict with a store instruction in the store queue that is older than the load instruction. The processor may remove the load instruction from the load queue while the store instruction remains in the store queue. The queue information may include a wrap value for the load queue.