Load Replay Precluding Mechanism for Out-of-Order Processor Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In out-of-order processors, the power wastage due to frequent load replays from non-core resources, such as L2 caches and fuse arrays, is significant, leading to increased power utilization and thermal issues, despite minimal performance impact, as these resources are shared among cores and access times are longer than on-core cache access.
Innovation Solution
Implementing a mechanism with reservation stations that detect specified load micro instructions directed to non-core resources, stalling younger dependent micro instructions until the load is completed, thereby reducing replays and enabling power management in execution units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load micro instructions are dispatched to execution units in out-of-order processors, then instruction throughput is improved, but power consumption increases due to frequent replays from non-core resources
Solution Approach 1:
The mechanism performs preliminary detection of load micro instructions targeting non-core resources before dispatching younger dependent instructions. By identifying these instructions in advance and stalling dependent instructions until load completion, the system prevents unnecessary executions and replays, thereby reducing power consumption while maintaining throughput for independent instructions
Solution Approach 2:
A hold bus acts as an intermediary communication channel between the first reservation station (detecting load instructions) and the second reservation station (dispatching younger instructions). This intermediary mechanism enables coordinated control where the hold bus signals when to stall dependent instructions, preventing power-wasting replays without blocking independent instruction flow
2Loss of time
If younger dependent micro instructions are dispatched immediately after load instructions, then execution latency is reduced, but replay frequency increases for instructions accessing non-core resources
Solution Approach 1:
The system performs preliminary detection of load instructions accessing non-core resources (L2 cache, fuse arrays) before dispatching younger dependent instructions. By stalling dependent instructions until the load operation completes, the mechanism ensures operands are available before execution, eliminating replays while maintaining low latency for instructions that don't require stalling
3Device complexity
If all load instructions are executed without differentiation, then simplicity is maintained, but power wastage occurs due to unnecessary replays from shared non-core resources
Solution Approach 1:
The mechanism applies differentiated handling to specific load instructions based on their target resources. Load instructions accessing non-core resources (L2 cache, fuse arrays) are detected and handled differently by stalling dependent instructions, while loads to on-core cache proceed normally. This localized differentiation eliminates power wastage without significantly increasing overall system complexity
Data Source
AI summary
An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an advanced programmable interrupt controller (APIC), configured to perform interrupt operations.