Load Segments for Sense Amplifier Reference in DRAM Arrays
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Solution Overview
Problem
Current dynamic random-access memory (DRAM) device arrays have unused memory cells at the edges due to border row segments not being connected to circuitry for data storage, resulting in inefficient use of space.
Innovation Solution
Implementing a semiconductor device with load segments that approximate the capacitance of bit line segments, allowing sense amplifiers adjacent to border segments to use these load segments as references during access operations, and employing tunable circuitry to adjust capacitance for improved sensing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If border row segments are used for data storage, then memory capacity increases, but sensing performance deteriorates because they lack proper reference circuitry
Solution Approach 1:
The patent creates a copy of the reference bit line segment structure by implementing load segments that replicate the capacitance characteristics of actual bit line segments. These copied structures provide the necessary reference functionality for border row segments without requiring full data storage circuitry, thus enabling both increased capacity and maintained sensing performance.
Solution Approach 2:
The load segments serve multiple functions: they provide reference capacitance for sensing operations, simulate the electrical characteristics of actual bit line segments, and enable border row segments to function as both data storage and reference sources. This multi-functionality resolves the contradiction by making the same structure serve both capacity expansion and reliability requirements.
2Reliability
If load segments are added to provide reference for border segments, then sensing performance improves, but device complexity increases
Solution Approach 1:
The patent adjusts the capacitance parameters of load segments to match those of actual bit line segments, creating electrical equivalence without structural duplication. By changing the capacitance parameter to match reference requirements, the patent achieves improved sensing performance while avoiding the complexity of adding full reference bit line segments.
Solution Approach 2:
The patent extracts only the essential reference functionality from full bit line segments by implementing simplified load segments that provide only the necessary capacitance for sensing operations. This extraction approach provides the needed reference capability while minimizing the added circuit complexity.
3Device complexity
If border row segments are left unused, then sensing performance is maintained with simple architecture, but area efficiency deteriorates
Solution Approach 1:
The patent makes border row segments multi-functional by enabling them to serve both as data storage locations and as reference sources for sensing operations. The load segments provide the reference capability, allowing border segments to be fully utilized for data storage while maintaining the simplicity of the overall architecture.
Solution Approach 2:
By copying the reference functionality through load segments, the patent enables border row segments to be used for data storage without complicating the architecture. The copied reference capability allows full utilization of array area while keeping the design relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the efficient use of memory cells at the edges of the array, enhancing data storage capacity and reducing waste space, thereby improving the overall performance and efficiency of DRAM devices.
Implementation Method 1
the load segment is configured to approximate a capacitance of the bit line segment
Data Source
AI summary
Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing. An example apparatus may include a memory array comprising a plurality of sense amplifiers. A first sense amplifier is coupled to a first access line segment and to a second access line segment and a second sense amplifier is coupled to a third access line segment and to a load segment. The first, second, and third access line segments are coupled to a respective plurality of memory cells. The load segment comprise load circuitry configured to provide a capacitive load to the second sense amplifier based on a capacitive load of the third access line segment.