Load-Modulated Signal Receiver With Two-Integrator Correlation
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Solution Overview
Problem
Existing RFID receiver designs occupy a large chip area and consume excessive energy due to the use of four integrators and complex post-processing of multiple output signals, which affects the quality of digital data.
Innovation Solution
The receiver is redesigned to utilize only two integrators by combining the outputs of the four subcarrier mixers through complex-valued number multiplication, reducing chip area and power consumption while improving signal amplitude and quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If four integrators are used to process outputs from four subcarrier mixers, then signal processing completeness is improved, but chip area and power consumption increase
Solution Approach 1:
The patent combines the outputs of four subcarrier mixers by treating them as complex-valued numbers, merging the processing into two integrators. This reduces the number of integrators from four to two, thereby reducing chip area and power consumption while maintaining signal processing completeness through complex number arithmetic that preserves all necessary signal information.
Solution Approach 2:
The patent changes the processing approach by representing subcarrier mixer outputs as complex-valued numbers with real and imaginary parts. This parameter transformation allows mathematical operations that combine multiple signals into fewer integrator outputs, achieving the same processing completeness with reduced hardware resources.
2Measurement precision
If four integrators and complex post-processing are used, then digital data quality is improved, but energy consumption increases
Solution Approach 1:
The patent merges the processing of four subcarrier mixer outputs into two integrators by using complex-valued number representation. This reduction in the number of integrators directly decreases energy consumption while the complex number processing methodology maintains the precision and quality of digital data output.
Solution Approach 2:
The patent replaces the physical hardware approach of using four separate integrators with a mathematical approach using complex-valued number operations. This substitution reduces the physical system complexity and energy requirements while maintaining the same processing capability and output quality.
3Reliability
If four subcarrier mixers are processed separately, then signal processing thoroughness is improved, but device complexity increases
Solution Approach 1:
The patent combines the separate processing paths of four subcarrier mixers into a unified complex-valued number processing framework. This merging reduces device complexity by eliminating redundant processing stages while maintaining thoroughness through the mathematical properties of complex number operations that preserve all signal characteristics.
Solution Approach 2:
The patent creates a universal processing approach where two integrators handle the processing of all four subcarrier mixer outputs through complex number arithmetic. This multi-functional approach reduces device complexity by making the integrators perform multiple processing functions simultaneously, while maintaining complete signal processing thoroughness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces complexity and energy consumption while enhancing the quality of digital data by combining the outputs of the correlators, resulting in improved signal amplitude and reduced packet error rates.
Implementation Method 1
an in-phase carrier mixer that mixes the input signal with an in-phase carrier frequency signal and provides an in-phase component of the down-converted input signal
Implementation Method 2
a quadrature-phase carrier mixer that mixes the input signal with a quadrature-phase carrier frequency signal and provides a quadrature-phase component of the down-converted input signal
Implementation Method 3
an amplifier to amplify the in-phase component and the quadrature-phase component of the down-converted input signal
Implementation Method 4
a DC block filter to remove the DC component of the in-phase component and the quadrature-phase component
Data Source
AI summary
A receiver (36; 43) that is built to receive a load modulated analog input signal (3) and built to output digital data (4) detected in the input signal (3), which receiver (36; 43) comprises: either a first in-phase correlator (38) and a second in-phase correlator (40) or a first quadrature-phase correlator (45) and a second quadrature-phase correlator (46),which first in-phase correlator (38) comprises:a first in-phase subcarrier mixer (23-1) and a first subtraction stage (39) built to subtract an output signal (28-2) of the second quadrature-phase subcarrier mixer (23-4) from an output signal (27-1) of the first in-phase subcarrier mixer (23-1) andan integrator (26) built to continuously integrate an output signal of the first subtraction stage (39) over time during an integration window to provide the output signal of the first in-phase correlator (38);which second in-phase correlator (40) comprises:a second in-phase subcarrier mixer (23-2) and an first addition stage (41) built to add an output signal (27-2) of the second in-phase subcarrier mixer (23-2) with an output signal (28-1) of the first quadrature-phase subcarrier mixer (23-3) andan integrator (26) built to continuously integrate an output signal of the first addition stage (41) over time during an integration window to provide the output signal of the second in-phase correlator (40).