Load Speculation via Dependence Prediction Tables

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Solution Overview

Problem

In computing systems, load instructions cannot be executed until the addresses of all store instructions in the pipeline have been determined, leading to potential mispredictions and performance issues when load instructions are executed ahead of older store instructions with the same target address, resulting in reading invalid data.

Innovation Solution

A processor system that includes a memory, instruction cache, and a dependence prediction unit, which allows load instructions to be speculatively issued ahead of store instructions by using tables to predict and manage dependencies, incrementing entries in misprediction detection tables, and invalidating instructions upon misprediction detection to prevent incorrect data reads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If load instructions are executed ahead of older store instructions to improve performance, then execution speed is improved, but data correctness deteriorates due to reading invalid data from same target address

Engineering Contradiction:
Improveexecution speedVSAvoiddata correctness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The processor performs preliminary actions by determining store instruction addresses before executing load instructions. The system pre-calculates and stores target addresses of store instructions in a data structure, allowing load instructions to be executed ahead of time while still ensuring data correctness by checking against the pre-determined store addresses.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A data structure acts as an intermediary between store and load instructions. This intermediate structure stores target addresses of store instructions and enables the processor to verify whether a load instruction's target address matches any pending store instruction's target address, thus preventing incorrect data reads while allowing out-of-order execution.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If load instructions wait for all store instruction addresses to be determined to ensure data correctness, then data correctness is maintained, but execution speed deteriorates due to waiting

Engineering Contradiction:
Improvedata correctnessVSAvoidexecution speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary determination of store instruction addresses and stores them in a data structure before load instructions need to execute. This preliminary action allows load instructions to proceed without waiting, while the pre-stored address information ensures data correctness can be verified.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically manages the execution order of instructions based on address determination status. Instead of a fixed waiting mechanism, the processor dynamically checks the data structure to determine whether a load instruction can safely execute ahead of store instructions, allowing flexible optimization of execution speed while maintaining correctness.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10073789B2Method for load instruction speculation past older store instructions
Publication Date: 2018.09.11 ORACLE INT CORP
  • US10073789B2 patent drawing
  • US10073789B2 patent drawing
  • US10073789B2 patent drawing

AI summary

A system includes a memory, a cache including multiple cache lines; and a processor. The processor may be configured to retrieve, from a first cache line, a first instruction to store data in a memory location at an address in the memory. The processor may be configured to retrieve, from a second cache line, a second instruction to read the memory location at the address in the memory. The second instruction may be retrieved after the first instruction. The processor may be configured to execute the second instruction at a first time dependent upon a value of a first entry in a table, wherein the first entry is selected dependent upon a value in the second cache line. The processor may be configured to execute the first instruction at a second time, after the first time, and invalidate the second instruction at a third time, after the second time.