Load-Store Instruction Fusion to Cut Processor Execution Latency
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Solution Overview
Problem
Existing processor architectures inefficiently execute load instructions in conjunction with other instructions, leading to increased execution latency and resource consumption due to separate handling of load results in different execution units.
Innovation Solution
Fusing load instructions with non-load instructions, such as conditional branch or ALU instructions, within the load/store unit to perform operations concurrently, reducing the need for forwarding load results to separate execution units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load instructions are executed separately in load/store units and results are forwarded to other execution units, then the processor can handle different instruction types in dedicated units, but execution latency increases and more clock cycles are consumed
Solution Approach 1:
The patent combines load instructions with subsequent non-load instructions (such as ALU operations or conditional branches) into a single fused instruction that executes entirely within the load/store unit. This merging eliminates the need to forward data between execution units and reduces execution latency by performing multiple operations in one clock cycle.
Solution Approach 2:
The load/store unit is enhanced to perform multiple functions: it can execute load instructions, ALU operations, and conditional branch instructions all within the same unit. This multi-functionality allows the load/store unit to handle fused instructions without requiring separate execution units, thereby reducing latency and improving throughput.
2Productivity
If load instructions are executed separately from other instructions, then execution units can be specialized for specific operations, but resource consumption increases due to multiple execution units being activated
Solution Approach 1:
By merging load instructions with subsequent ALU or branch operations into a single fused instruction, the patent activates only the load/store unit for the entire operation sequence. This reduces the number of active execution units, thereby lowering power consumption while maintaining execution efficiency.
Solution Approach 2:
The load/store unit is designed with multi-functionality to handle load operations, ALU operations, and branch operations within a single unit. This eliminates the need to activate multiple specialized execution units, reducing overall resource consumption and power usage while improving execution efficiency.
3Productivity
If load results are forwarded to separate execution units for further operations, then specialized execution units can perform their designated functions, but additional resources and forwarding mechanisms are required
Solution Approach 1:
The patent merges load instructions with subsequent operations into fused instructions that execute entirely within the load/store unit. This eliminates the need for complex data forwarding mechanisms between execution units, reducing device complexity while preserving full instruction execution capability.
Solution Approach 2:
The load/store unit is enhanced with multi-functionality to perform load operations, ALU operations, and branch operations within a single unit. This consolidation eliminates the need for inter-unit forwarding mechanisms and associated complexity, while maintaining comprehensive instruction execution capability.
Data Source
AI summary
Techniques are disclosed that relate to executing fused instructions. A processor may include a decoder circuit and a load/store circuit. The decoder circuit may detect a load/store instruction to load a value from a memory and detect a non-load/store instruction that depends on the value to be loaded. The decoder circuit may fuse the load/store instruction and the non-load/store instruction such that one or more operations that the non-load/store instruction is defined to perform are to be executed within the load/store circuit. The load/store circuit may receive an indication of the fused load/store and non-load/store instructions and then execute one or more operations of the load/store instruction and the one or more operations of the non-load/store instruction using a circuit included in the load/store circuit.