Load Store Queue Allocation at Address Generation Time
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Solution Overview
Problem
The depth of load and store queues in processors limits the effective window size, causing dispatch stalls when these queues are full, and existing solutions struggle to efficiently manage micro-operation dispatch and address generation, leading to architectural congestion and timing issues.
Innovation Solution
Implementing a method where micro-operations are dispatched to a scheduler queue at address generation time, delaying queue entry allocation until available, and using age-ordering and wrap bits to manage queue entries, allowing for increased dispatch of store micro-ops beyond the queue depth without architectural congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load and store queue depth is increased to enable higher instructions per clock, then processing capacity is improved, but timing problems and architectural congestion occur
Solution Approach 1:
The patent segments the queue entry allocation process into two distinct phases: dispatch-time allocation of queue identifiers and address-generation-time allocation of actual queue entries. This segmentation allows the dispatch stage to proceed without waiting for queue entry availability, while address generation occurs only when entries are free, thereby increasing IPC without causing timing conflicts.
Solution Approach 2:
The patent performs preliminary allocation of queue identifiers at dispatch time, before actual queue entry allocation is needed. This preliminary action allows the instruction to be dispatched and tracked without immediately consuming a queue entry, enabling higher throughput while avoiding timing problems by deferring the actual entry allocation until address generation time.
2Productivity
If load and store queue depth is increased to expand the effective window size, then more instructions can be processed simultaneously, but dispatch stalls occur when queues are full
Solution Approach 1:
The patent introduces an intermediary mechanism where queue identifiers are allocated at dispatch time but actual queue entry allocation is deferred until address generation time. This intermediary approach allows the dispatch stage to proceed without stalls by using placeholder identifiers, while the actual entry allocation happens later when entries are available, thus increasing parallel processing capacity without dispatch stalls.
3Productivity
If queue entry allocation is delayed until address generation time, then dispatch window size increases, but complexity of managing queue entries increases
Solution Approach 1:
The patent implements a dynamic queue entry management system where the allocation of actual queue entries is deferred until address generation time based on availability. The system dynamically adjusts which instructions receive queue entries based on current queue state, allowing the dispatch window to expand beyond the physical queue depth while maintaining orderly execution through age-order tracking and wrap bit management.
4Productivity
If more store micro-ops are dispatched beyond queue depth, then processing throughput increases, but architectural congestion occurs
Solution Approach 1:
The patent segments the store micro-op processing into dispatch-time identifier allocation and address-generation-time entry allocation. This segmentation allows multiple store micro-ops to be dispatched beyond the physical queue depth by using placeholder identifiers, while actual entry allocation occurs later when queue entries are available, increasing throughput without causing architectural congestion.
Data Source
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AI summary
A system and method for load queue (LDQ) and store queue (STQ) entry allocations at address generation time that maintains age-order of instructions is described. In particular, writing LDQ and STQ entries are delayed until address generation time. This allows the load and store operations to dispatch, and younger operations (which may not be store and load operations) to also dispatch and execute their instructions. The address generation of the load or store operation is held at an address generation scheduler queue (AGSQ) until a load or store queue entry is available for the operation. The tracking of load queue entries or store queue entries is effectively being done in the AGSQ instead of at the decode engine. The LDQ and STQ depth is not visible from a decode engine's perspective, and increases the effective processing and queue depth.