Out-of-Order Processor Load Store Reordering via Instruction Splitting
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Solution Overview
Problem
Current processor architectures face inefficiencies in context switching and parallelism due to the overhead of duplicating architecture state elements for multiple threads, particularly in fine-grained parallelism scenarios, where context switches are frequent and resource-intensive, and existing techniques struggle to efficiently execute load and store operations in out-of-order processors.
Innovation Solution
The method involves splitting store and load instructions into address calculation and data transfer components, allowing for earlier dispatch and execution by reordering these instructions, enabling speculative execution while maintaining memory consistency through a unified load/store queue and speculative recovery mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If hardware duplicates all architecture state elements for each supported thread, then context switch overhead is eliminated for hardware-supported threads, but area, power and complexity increase significantly
Solution Approach 1:
The architecture state is segmented into multiple save areas (first save area, second save area, third save area) that can be selectively used. Instead of duplicating the entire architecture state for each thread, the system divides the state into manageable segments that can be stored and switched between efficiently.
Solution Approach 2:
The architecture state is pre-saved into different save areas before context switching is needed. The system prepares multiple save areas in advance, allowing for rapid context switching without the overhead of saving and restoring state during the actual context switch operation.
2Productivity
If the number of software threads exceeds the number of explicitly supported hardware threads, then fine-grained parallelism is enabled, but context switches must still be performed increasing overhead
Solution Approach 1:
The system segments the thread management into multiple save areas that can accommodate more software threads than hardware threads. This segmentation allows fine-grained parallelism by enabling multiple thread contexts to be maintained and switched between without requiring proportional hardware thread duplication.
Solution Approach 2:
The architecture uses copied state representations in different save areas to represent multiple thread contexts. Instead of requiring unique hardware resources for each thread, the system creates copies of the architecture state in different save areas, enabling efficient context switching for fine-grained parallelism.
3Reliability
If load and store instructions are executed in program order, then memory consistency is maintained, but execution latency increases in out-of-order processors
Solution Approach 1:
Address calculation for load and store instructions is performed in advance (preliminarily) before the actual data transfer. The system calculates addresses early in the instruction pipeline, allowing the data transfer operations to proceed without waiting for address computation, thus reducing overall execution latency while maintaining memory consistency through proper ordering of the address calculation results.
Data Source
AI summary
A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions, and of said sequence of instructions, splitting store instructions into a store address instruction and a store data instruction, wherein the store address performs address calculation and fetch, and wherein the store data performs a load of register contents to a memory address. The method further includes, of said sequence of instructions, splitting load instructions into a load address instruction and a load data instruction, wherein the load address performs address calculation and fetch, and wherein the load data performs a load of memory address contents into a register, and reordering the store address and load address instructions earlier and further away from LD/SD the instruction sequence to enable earlier dispatch and execution of the loads and the stores.