Load-Store Unit Effective Address Synonym Handling
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Solution Overview
Problem
In out-of-order processors, tracking effective addresses leads to inefficiencies in chip area and power consumption due to the need for extensive address translation and storage structures, particularly in handling data hazards and branch instructions across multiple stages of the pipeline.
Innovation Solution
Implementing an effective address directory (EAD) with an effective real translation (ERT) table and an effective real translation eviction (ERTE) table to manage effective addresses, reducing the need for real address translation within the out-of-order window and minimizing chip area and power consumption by policing against effective address synonyms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If real address translation is performed for every effective address in the out-of-order window, then address translation accuracy is improved, but chip area and power consumption increase
Solution Approach 1:
The patent extracts only the necessary address translation functionality by implementing an effective real translation (ERT) table that stores mappings between effective addresses and real addresses. Instead of performing full address translation for every effective address, the system selectively translates only those addresses that are actually needed for memory access, removing unnecessary translation overhead and reducing chip area requirements.
Solution Approach 2:
The patent applies local quality by implementing an effective real translation eviction (ERTE) table that maintains translation information locally within the load-store unit. This localized translation cache provides quick access to recent address mappings without requiring global address translation resources, optimizing the balance between translation accuracy and resource utilization in specific regions of the processor.
2Measurement precision
If real address translation is performed for every effective address, then address translation completeness is improved, but power consumption increases
Solution Approach 1:
The patent implements partial action by performing address translation only when necessary - specifically when an effective address needs to be accessed in the out-of-order window. The ERT table stores only the translations that are currently needed, and the ERTE table evicts translations that are no longer required. This selective translation approach maintains completeness for active addresses while avoiding the excessive power consumption of translating all possible addresses continuously.
3Adaptability or versatility
If extensive address translation structures are implemented, then address mapping capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the address translation functionality into two distinct components: the ERT table for storing active effective-to-real address mappings, and the ERTE table for managing eviction of inactive mappings. This segmentation allows each component to be optimized independently - the ERT table focuses on providing accurate translations while the ERTE table handles the complexity of managing translation lifecycle, thereby reducing overall device complexity through functional decomposition.
4Reliability
If effective addresses are tracked throughout the pipeline, then hazard detection capability is improved, but chip area increases
Solution Approach 1:
The patent introduces the ERT table as an intermediary structure between the effective address generation stage and the memory access stage. This intermediary table stores the mapping relationships needed for hazard detection without requiring extensive tracking of effective addresses throughout the entire pipeline. By using the ERT table as a mediator, the system can detect hazards accurately while minimizing the chip area required for address tracking infrastructure.
Data Source
AI summary
Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window. The issuing includes, in response to determining a first effective address (EA) being used by a first instruction, the first EA corresponding to a first real address (RA), creating a first effective real translation (ERT) table entry in an ERT table, the ERT entry mapping the first EA to the first RA. Further, in response to determining an EA synonym used by a second instruction, the execution includes replacing the first ERT entry with a second ERT entry, wherein the second ERT entry maps the second EA with the first RA, and creating an ERT eviction (ERTE) table entry in an ERTE table, wherein the ERTE entry maps the first RA to the first EA, the ERTE table entry maintains the relationship between the first EA and the first RA.