Load Store Unit Flush Avoidance via ERAT Tracking
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Solution Overview
Problem
In computer processors, flush operations in load/store units often result in inefficiencies due to the need to halt dispatch of new instructions and discard information when rejection conditions occur, such as address misses or cache collisions, leading to wasted cycles and resource usage.
Innovation Solution
Implementing a load/store slice that maintains tracking of instructions during rejection conditions, allowing for immediate reissue upon resolution, reducing resource usage and avoiding unnecessary notifications to the instruction sequencing unit, and using a data valid message system to verify cache entries during ERAT updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a flush operation is performed in the load/store unit due to rejection conditions (address misses or cache collisions), then the incorrect instructions are discarded, but the dispatch of new instructions is halted and information is discarded, leading to wasted cycles and reduced productivity
Solution Approach 1:
The load/store unit performs preliminary tracking of instructions during ERAT updates before a flush is required. By maintaining a record of instructions in flight and their associated cache addresses, the system prepares for potential flush conditions in advance, allowing for faster recovery and reducing the impact on instruction throughput when rejection conditions occur
Solution Approach 2:
Instead of discarding all instruction information during a flush operation, the system recovers useful information by tracking which instructions are affected by the flush condition. The load/store unit identifies specific instructions that need to be flushed while preserving information about other instructions that can continue execution, thereby reducing wasted cycles and improving overall productivity
2Reliability
If the load/store unit notifies the instruction sequencing unit of rejection conditions, then the instruction sequencing unit can handle the error, but resource usage increases and cycles are wasted due to the notification overhead and halting of dispatch
Solution Approach 1:
The system extracts the tracking and verification functionality from the instruction sequencing unit and places it directly in the load/store unit. By taking out the ERAT update tracking and cache entry verification responsibilities from the instruction sequencing unit, the system eliminates the need for notifications and halting, allowing the load/store unit to independently manage rejection conditions and continue instruction dispatch without interruption
Solution Approach 2:
The load/store unit performs self-service by independently tracking its own instructions during ERAT updates and verifying cache entries without external intervention. This self-service capability allows the unit to handle rejection conditions autonomously, eliminating the overhead of notifying the instruction sequencing unit and reducing the loss of execution cycles
3Reliability
If the system performs full verification of cache entries during ERAT updates, then data validity is ensured, but the complexity of the verification process increases and additional resources are consumed
Solution Approach 1:
The system performs partial verification by tracking only the specific cache entries that are relevant to instructions currently in flight during ERAT updates. Instead of verifying all cache entries in the system, the load/store unit focuses verification efforts on the subset of entries that could potentially affect instruction execution, thereby reducing complexity and resource consumption while maintaining data validity assurance for critical operations
Data Source
AI summary
Flush avoidance in a load store unit including launching a load instruction targeting an effective address; encountering a set predict hit and an effective-to-real address translator (ERAT) miss for the effective address, wherein the set predict hit comprises a cache address of a cache entry; sending a data valid message for the load instruction to an instruction sequencing unit; and verifying the data valid message, wherein verifying the data valid message comprises: tracking the cache entry during an ERAT update; and upon completion of the ERAT update, encountering an ERAT hit for the effective address in response to relaunching the load instruction.