Load-Store Unit Partitioned Reorder Queues Single CAM Port
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Solution Overview
Problem
Out-of-order processors face inefficiencies in tracking effective addresses, leading to increased chip area and power consumption due to the need for multiple content addressable memory (CAM) ports for address translation, especially in multi-threaded environments where multiple threads require separate CAM ports for each load/store queue.
Innovation Solution
Implementing an effective address (EA) based load-store unit with a single CAM port using an effective address directory (EAD), effective real table (ERT), and synonym detection table (SDT) to reduce chip area and power consumption by policing against EA synonyms within the out-of-order window, allowing for partitioned load/store queues and minimizing CAM ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple CAM ports are used for address translation in multi-threaded environments, then address translation efficiency is improved, but chip area and power consumption increase
Solution Approach 1:
The load reorder queue is divided into multiple partitions, with each partition handling address translation for specific threads or pipes. This segmentation allows the system to use fewer CAM ports overall while maintaining address translation efficiency for each thread, as each partition can independently manage its own address translation needs without requiring dedicated CAM ports for every thread.
Solution Approach 2:
The patent implements a unified address translation mechanism that serves multiple threads and pipes through shared CAM ports. The load reorder queue partitions are designed to be universal, allowing the same CAM port to be reused across different threads and pipes, thereby reducing the total number of CAM ports required while maintaining address translation functionality for all threads.
2Measurement precision
If multiple CAM ports are used for address translation in multi-threaded environments, then address translation efficiency is improved, but power consumption increases
Solution Approach 1:
By segmenting the load reorder queue into partitions that can be independently managed, the system activates only the necessary CAM ports for currently active threads, reducing overall power consumption compared to having all CAM ports continuously active.
Solution Approach 2:
The universal address translation mechanism allows CAM ports to be shared across multiple threads, reducing the total number of CAM ports needed and thereby reducing the cumulative power consumption of the address translation subsystem.
3Productivity
If partitioned load/store queues are implemented, then out-of-order execution efficiency is improved, but device complexity increases
Solution Approach 1:
The load reorder queue is segmented into multiple partitions, each handling specific threads or pipes. This segmentation enables efficient out-of-order execution by allowing independent management of instructions from different threads, improving productivity while keeping each partition relatively simple in structure.
4Area of stationary object
If a single CAM port is used, then chip area and power consumption are reduced, but address translation efficiency may deteriorate
Solution Approach 1:
By segmenting the load reorder queue into partitions, the system can use a single CAM port per partition rather than requiring multiple CAM ports for every thread. This segmentation maintains address translation efficiency within each partition while significantly reducing the total chip area and power consumption.
Solution Approach 2:
The unified address translation mechanism allows a single CAM port to serve multiple threads through time-multiplexed access, maintaining address translation efficiency while reducing the number of physical CAM ports required, thereby reducing chip area and power consumption.
Data Source
AI summary
Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.