Load Store Execution Unit Reconfiguration for Single-Thread Performance
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Solution Overview
Problem
Existing microprocessor architectures face inefficiencies in single-thread mode due to limited use of load/store execution units, leading to reduced instructions per cycle and increased stalling when waiting for external resources.
Innovation Solution
The microprocessor is configured to reconfigure its second load/store execution unit to assist the first unit in single-thread mode, allowing for increased instructions per cycle by effectively merging the two units and utilizing them as a single, enhanced execution unit, while maintaining independence in multi-thread mode to handle multiple threads efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-thread mode is used with traditional load/store execution unit configuration, then the processor structure is simple and easy to control, but the instructions per cycle are limited and processing efficiency is reduced
Solution Approach 1:
The patent merges the second load/store execution unit with the first load/store execution unit in single-thread mode, allowing them to function as a unified execution resource. This merging enables the processor to issue and execute multiple load/store instructions per cycle (up to three instructions per cycle) while maintaining a relatively simple control structure, thereby resolving the contradiction between productivity and device complexity.
2Productivity
If multiple load/store execution units are used independently in single-thread mode, then the instructions per cycle can be increased, but the control complexity and resource waste increase
Solution Approach 1:
The patent implements dynamic configuration of the load/store execution units based on the operating mode. In single-thread mode, the units are merged and coordinated to execute instructions together, maximizing utilization. In multi-thread mode, they operate independently. This dynamic adaptation eliminates energy waste from idle execution units while maintaining high instructions per cycle capability, resolving the contradiction between productivity and energy loss.
3Productivity
If traditional single execution unit configuration is used, then the device complexity is low and control is easy, but the processor stalls frequently when waiting for external resources
Solution Approach 1:
By merging the functionality of multiple load/store execution units in single-thread mode, the patent enables parallel execution of multiple memory access instructions. This reduces stalling time when waiting for external resources because the processor can issue multiple load/store instructions in parallel rather than sequentially, thereby improving processing efficiency without significantly increasing control complexity.
4Productivity
If the second load/store execution unit is reconfigured to assist the first unit in single-thread mode, then the instructions per cycle increase to three, but the control logic becomes more complex
Solution Approach 1:
The patent uses dynamic reconfiguration control that activates the second load/store execution unit's assistance functionality only when needed (in single-thread mode). The control logic detects the operating mode and selectively enables the merged execution configuration, allowing up to three instructions per cycle. This dynamic approach minimizes control logic complexity by not permanently enabling all features, thereby resolving the contradiction between productivity and device complexity.
Data Source
AI summary
Systems and methods are disclosed for multi-threading computer systems. In a computer system executing multiple program threads in a processing unit, a first load/store execution unit is configured to handle instructions from a first program thread and a second load/store execution unit is configured to handle instructions from a second program thread. When the computer system executing a single program thread, the first and second load/store execution units are reconfigured to handle instructions from the single program thread, and a Level 1 (L1) data cache is reconfigured with a first port to communicate with the first load/store execution unit and a second port to communicate with the second load/store execution unit.