Low-Power Test Compression for LOC Transition Faults
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Solution Overview
Problem
Current commercial EDA tools fail to effectively handle test compression for LOC delay testing, leading to excessive test power dissipation and large test data volumes, which is more challenging than single stuck-at fault testing.
Innovation Solution
A new low-power test compression architecture is proposed, incorporating a LFSR established by a selected primitive polynomial and extra variables, a scan tree architecture, a new gating technique, and a static test compaction scheme, along with test point insertion in the two-frame-circuit model to reduce test data volume and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional test compression methods are used for LOC delay testing, then fault coverage is achieved, but test power dissipation becomes excessive and test data volume remains large
Solution Approach 1:
The test compression architecture segments the test data flow into multiple parallel scan chains, each processing a portion of the test patterns. This segmentation allows selective activation of scan chains based on test requirements, reducing overall power dissipation while maintaining comprehensive fault coverage through distributed test pattern application.
Solution Approach 2:
The architecture implements periodic test pattern application through controlled scan chain activation, where scan chains are enabled in alternating phases rather than continuously. This periodic action reduces average power consumption during test application while ensuring all circuits receive necessary test coverage over complete test cycles.
2Reliability
If traditional test compression methods are used for LOC delay testing, then fault coverage is achieved, but test data volume remains large
Solution Approach 1:
Multiple scan chains are merged into a unified test compression architecture that shares common control logic and pattern generation resources. This merging reduces redundant test data storage and transmission requirements while maintaining the ability to independently activate each scan chain for comprehensive fault coverage.
Solution Approach 2:
The test compression architecture implements universal pattern generation capabilities that can produce different test patterns for different scan chains using shared resources. This multi-functionality reduces overall test data volume by eliminating the need for separate dedicated pattern storage for each scan chain, while still achieving complete fault coverage.
3Measurement precision
If more test patterns are applied to improve LOC delay fault coverage, then fault detection capability increases, but test power dissipation increases
Solution Approach 1:
The architecture dynamically configures scan chain activation based on test progress and coverage requirements. Rather than statically enabling all scan chains throughout testing, the system adaptively activates only the necessary scan chains at each phase, maintaining high fault detection capability while minimizing instantaneous power dissipation through dynamic resource allocation.
4Quantity of substance
If test compression is applied to reduce test data volume, then storage requirements decrease, but test application complexity increases
Solution Approach 1:
The test compression architecture performs preliminary organization of test patterns during the design phase, pre-configuring scan chain groupings and control logic structures. This preliminary action simplifies subsequent test application by eliminating the need for complex runtime decision-making, reducing test application complexity while maintaining effective data compression.
Data Source
AI summary
A new low-power test compression method and design for testability (DFT) architecture are proposed for deterministic test pairs for launch-on-capture (LOC) transition fault testing by using a new seed encoding scheme, a new low-power test application procedure and a new test compression architecture. The new seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set. The low-power test compression architecture includes: (1) the LFSR established by the selected primitive polynomial and the selected number of extra variables injected to the LFSR; (2) the scan tree architecture for LOC transition fault testing; and (3) the new gating technique. A new static test compaction scheme is proposed by bitwise modifying the values of a seed and the extra variables. A new technique for test point insertion is proposed for LOC delay testing in the two-frame-circuit model, which apparently reduces test data volume.