Local BIST Circuits for High-Speed Memory Testing
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Solution Overview
Problem
In integrated circuits with distributed memory blocks, centralized built-in-self-test (BIST) circuits face challenges in satisfying timing requirements due to long routing distances, making high-speed memory tests difficult and inefficient.
Innovation Solution
Implementing local BIST circuits within each sector of the integrated circuit, each with a local sector manager controller and BIST enabled wrapper circuits, allows for direct testing of memory circuits at higher frequencies, reducing the need for long signal paths and enabling at-speed testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If centralized BIST circuits are used to test distributed memory blocks, then a single test circuit can cover multiple memory blocks, but the long routing distances prevent satisfaction of timing requirements for high-speed testing
Solution Approach 1:
The patent divides the centralized BIST circuit into multiple local BIST circuits, each assigned to specific memory blocks. This segmentation reduces the routing distance between the BIST circuit and memory blocks, enabling timing closure for high-speed testing while maintaining comprehensive test coverage across distributed memory blocks.
Solution Approach 2:
The patent places BIST circuits locally within or near the memory blocks they test, rather than using a single centralized location. This local placement optimizes the routing characteristics for each specific test relationship, ensuring that timing requirements are met for high-speed testing of each memory block by its nearby BIST circuit.
2Speed
If local BIST circuits are implemented in each sector, then timing requirements can be satisfied for high-speed testing, but the overall device complexity increases
Solution Approach 1:
While segmentation into local BIST circuits does increase the number of test circuits, it eliminates the need for complex long-distance routing and enables straightforward high-speed testing. The modular segmented structure simplifies the overall system architecture by making each local BIST-memory block pair self-contained and independently optimizable.
3Ease of manufacture
If centralized BIST circuits are used, then manufacturing cost may be lower due to fewer test circuits, but the long signal paths make high-speed testing difficult and inefficient
Solution Approach 1:
The segmentation into local BIST circuits enables efficient high-speed testing that can be performed in parallel across multiple memory blocks, significantly improving testing productivity. Although this increases the number of BIST circuits compared to a centralized approach, the parallel testing capability and reduced routing complexity result in overall manufacturing efficiency gains.
Data Source
AI summary
An integrated circuit includes sectors of logic circuits. Each of the sectors of logic circuits includes a local sector manager controller circuit that provides an indication to perform a memory test. Each of the sectors also includes a built-in-self-test circuit that is configurable to generate a control signal and expected data in response to the indication to perform the memory test. Each of the sectors also includes a memory circuit that outputs read data in response to the control signal during the memory test. Each of the sectors further includes a comparator circuit configurable to compare the read data with the expected data during the memory test to generate a test result that is provided to the built-in-self-test circuit.