Local Bitline IMC Memory Array for 2.2 GHz Read Stability
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Solution Overview
Problem
Current SRAM-based In-Memory Computing (IMC) solutions face challenges such as slow operation, high energy consumption, and read disturb issues, limiting their effectiveness in data-intensive applications like artificial intelligence and real-time video streaming, particularly due to the limitations of 6T SRAM bitcells which suffer from data corruption and reduced speed.
Innovation Solution
The proposed solution involves a local bitline-based IMC architecture with a memory array organized into local groups, using 6T SRAM bitcells connected to local and global bitlines, a precharge circuit, and a fast carry adder based on a dynamic Manchester Carry Chain, enabling simultaneous read and write operations without data corruption and supporting a wide voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 6T SRAM bitcells are used for in-memory computing, then area efficiency is improved, but read disturb data corruption occurs
Solution Approach 1:
The memory array is divided into multiple local groups, each with its own local bitlines and precharge circuits. This segmentation allows independent control of read operations in different regions, enabling selective precharging that prevents read disturb corruption while maintaining 6T bitcell area efficiency.
Solution Approach 2:
Local precharge circuits are implemented that activate before read operations to precharge local bitlines. This preliminary action ensures bitlines are properly charged before accessing bitcells, preventing read disturb data corruption while using compact 6T SRAM structures.
2Device complexity
If conventional SRAM architectures are used, then simplicity is maintained, but operation speed is limited to below 1 GHz
Solution Approach 1:
The memory is organized into local groups with local bitlines and precharge circuits, creating a hierarchical structure that reduces signal propagation delays. This segmentation enables operation frequencies up to 2.2 GHz while maintaining architectural simplicity through modular design.
Solution Approach 2:
Local precharge circuits are positioned between local bitlines and global bitlines, adding a spatial dimension to the precharge operation. This dimensional organization allows parallel precharging of multiple local groups, significantly increasing operation speed while keeping the overall architecture simple.
3Reliability
If 10T SRAM bitcells are used to avoid read disturb issues, then reliability is improved, but area efficiency decreases by at least 2×
Solution Approach 1:
The memory array is segmented into local groups with dedicated precharge circuits. This segmentation enables the use of compact 6T bitcells while achieving reliability comparable to or exceeding 10T bitcells through controlled precharging that prevents read disturb corruption.
Solution Approach 2:
Instead of using larger 10T bitcells, the invention copies the functionality of read-disturb-free operation to 6T bitcells through additional precharge circuitry. This approach achieves the same reliability benefit while maintaining the area efficiency of 6T structures.
4Use of energy by moving object
If analog capacitive adders are used for in-memory computing, then energy efficiency is improved, but operation speed decreases and variability increases
Solution Approach 1:
The invention replaces analog capacitive adder mechanisms with digital logic-based in-memory computing operations. This substitution eliminates the speed limitations and high variability of analog approaches while maintaining energy efficiency through direct bitline computing operations at frequencies up to 2.2 GHz.
Data Source
AI summary
A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.