Local Boosted Channel Inhibit Scheme for NAND Flash Program Disturb

Solution Overview

Problem

Existing NAND Flash memory program disturb inhibit schemes face challenges in minimizing unintended threshold voltage shifts during programming, leading to performance degradation and restrictions in random page programming due to high power consumption and increased chip size.

Innovation Solution

A local boosted channel inhibit scheme is implemented, where the selected memory cell is decoupled from other cells, allowing for a reduced pass voltage and efficient local boosting to prevent unintended programming, enabling random page programming while minimizing program disturb.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a high pass voltage is used to inhibit program disturb in unselected memory cells, then program disturb is minimized, but power consumption increases and chip size increases

Engineering Contradiction:

Improveprogram disturb inhibitionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the memory string into selected and unselected portions, applying different voltage strategies to each. The selected memory cell receives the full program voltage for programming, while unselected memory cells receive a reduced pass voltage that is sufficient to inhibit program disturb but consumes less power and requires smaller circuitry to generate.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing different voltage levels to different portions of the memory array. Specifically, the selected memory cell receives a high program voltage for programming, while unselected memory cells receive a lower pass voltage that is optimized for inhibit functionality rather than full programming capability, reducing overall power consumption and chip size requirements.

Inventive Principle:

Principle #3Local quality

2Reliability

If a high pass voltage is used to inhibit program disturb in unselected memory cells, then program disturb is minimized, but chip size increases

Engineering Contradiction:

Improveprogram disturb inhibitionVSAvoidchip size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the memory string into selected and unselected portions, applying different voltage strategies to each. The selected memory cell receives the full program voltage for programming, while unselected memory cells receive a reduced pass voltage that is sufficient to inhibit program disturb but consumes less power and requires smaller circuitry to generate.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing different voltage levels to different portions of the memory array. Specifically, the selected memory cell receives a high program voltage for programming, while unselected memory cells receive a lower pass voltage that is optimized for inhibit functionality rather than full programming capability, reducing overall power consumption and chip size requirements.

Inventive Principle:

Principle #3Local quality

3Use of energy by moving object

If a reduced pass voltage is used, then power consumption and chip size decrease, but program disturb in unselected memory cells increases

Engineering Contradiction:

Improvepower consumptionVSAvoidprogram disturb inhibition

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-charging the channel of unselected memory cells to a voltage level that inhibits program disturb before the program operation begins. This pre-charging is performed using the reduced pass voltage, which is sufficient to establish the inhibit condition in advance, allowing the subsequent programming operation to proceed without affecting unselected cells.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent employs dynamic voltage control where the pass voltage applied to unselected memory cells is dynamically adjusted during the programming operation. The voltage is applied in a time-dependent manner, being present during the pre-charge phase to inhibit program disturb but reduced or removed during the actual programming phase to avoid interfering with the selected cell programming.

Inventive Principle:

Principle #15Dynamics

4Reliability

If conventional inhibit schemes are used, then program disturb is reduced, but random page programming is restricted

Engineering Contradiction:

Improveprogram disturb inhibitionVSAvoidrandom page programming capability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the memory string into selected and unselected portions, applying different voltage strategies to each. The selected memory cell receives the full program voltage for programming, while unselected memory cells receive a reduced pass voltage that is sufficient to inhibit program disturb but consumes less power and requires smaller circuitry to generate.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic voltage control where the pass voltage applied to unselected memory cells is dynamically adjusted during the programming operation. The voltage is applied in a time-dependent manner, being present during the pre-charge phase to inhibit program disturb but reduced or removed during the actual programming phase to avoid interfering with the selected cell programming.

Inventive Principle:

Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces program disturb in unselected memory cells, allows for random page programming, and decreases power consumption and chip size by using a lower pass voltage, enhancing the efficiency and performance of NAND Flash memory programming.

Implementation Method 1

The selected memory cell channel is locally boosted to a secondary boosted voltage level after the channel is precharged

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Implementation Method 2

Flash memory is indirectly used by consumers in products such as cell phones and devices with microprocessing functions

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Data Source

PatentUS8300468B2Flash memory program inhibit scheme

Publication Date: 2012.10.30 MOSAID TECH

AI summary

A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.