Local Cache Power Control in Multiprocessor Systems
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Solution Overview
Problem
In multiprocessor systems, migrating processing tasks leads to power inefficiency due to the need to refetch data from main memory after powering down a processor, as dirty data in the local cache memory is not efficiently flushed or managed, wasting power and reducing the benefits of processor downscaling.
Innovation Solution
A cache power controller maintains power to local cache memories until a predetermined condition is met, switching them to a low power state where data is no longer accessible, thereby conserving power while ensuring data integrity and coherence through cache coherency controllers and processor power controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the local cache memory is flushed to main memory to enable processor power down, then data coherence is maintained, but power consumption increases and performance decreases due to refetching
Solution Approach 1:
The cache coherency controller performs preliminary actions by snooping memory access requests before the processor is fully powered down. It identifies dirty data in the local cache and proactively transfers it to other caches or main memory, ensuring data coherence is established before power reduction occurs. This preliminary action eliminates the need for complete cache flushing after power down.
Solution Approach 2:
The system implements feedback through the cache coherency controller that continuously monitors cache state and memory access patterns. When a processor is scheduled for power down, the controller receives feedback about which cache lines are dirty and uses this information to selectively maintain or flush only the necessary data, rather than flushing the entire cache. This feedback mechanism enables intelligent power management while maintaining coherence.
2Reliability
If the local cache memory is left powered up to maintain data accessibility, then data coherence is maintained, but power consumption increases
Solution Approach 1:
The system applies local quality by treating different cache lines differently based on their state and usage. Instead of uniformly powering up the entire cache, the cache coherency controller identifies specific dirty cache lines and maintains power only for those regions or uses selective retention mechanisms. This localized approach ensures data accessibility where needed while reducing power consumption in other areas.
Solution Approach 2:
The system changes the power state parameter of the cache memory dynamically based on processor activity and cache content. When a processor is powered down, the cache transitions from a fully powered state to a reduced power state for retained data, using parameters like retention mode or selective power gating. This parameter change enables the cache to maintain essential data with lower power consumption.
3Use of energy by moving object
If processing tasks are migrated to facilitate processor power down, then power consumption decreases, but data refetching from main memory increases power usage
Solution Approach 1:
The cache coherency controller extracts dirty data from the local cache of the processor being powered down and transfers it to other processors' caches or to main memory before power reduction. This extraction operation removes the problematic data that would otherwise require refetching, allowing the processor to be safely powered down without subsequent performance penalties or power-wasting refetch operations.
Data Source
AI summary
A data processing system including a plurality of processors 4, 6, 8 each having a local cache memory 10, 12, 14 is provided. A cache coherency controller 16 serves to maintain cache coherency between the local cache memories 10, 12, 14. When one of the processors 4, 6, 8 is placed into a low power state its associated local cache memory 10, 12, 14 is maintained in a state in which the data it is holding is accessible to the cache coherency controller 16 until a predetermined condition has been met whereupon the local cache memory 10, 12, 14 concerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.