Local Cell-Level Power Gating Switches for IC Voltage Droop Reduction
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Solution Overview
Problem
Standard power gating techniques in integrated circuit chips result in voltage droops and increased power consumption due to large switching devices and long interconnect lines, which are inefficient and lead to potential timing violations.
Innovation Solution
Implementing local cell-level power gating switches, each integrated with logic cells using thin-film transistor technologies, allowing for fine-tuned power management and reduced interconnect loads, thereby minimizing voltage droops and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single large switching device is used for power gating, then power can be provided to a large section of logic, but voltage droops occur and power consumption increases
Solution Approach 1:
The patent divides the single large power gating switch into multiple smaller local power switches, each serving a specific logic cell or small group of cells. This segmentation reduces the capacitive load each switch must charge/discharge, minimizing voltage droops and reducing dynamic power consumption associated with switching large interconnect capacitances.
Solution Approach 2:
The patent transitions from a global power gating approach to a local cell-level approach by adding spatial granularity. Each logic cell gets its own dedicated power switch located immediately adjacent to it, eliminating the need for long interconnect lines and reducing the dimensional distance between power source and load.
2Reliability
If large interconnect lines are used to connect power switches to all loads, then voltage droops are prevented, but power consumption increases and device complexity increases
Solution Approach 1:
The patent extracts the power switching function from a centralized location and places it directly at each logic cell. This eliminates the need for large interconnect lines spanning across the chip, as each cell's power switch only needs to connect to its immediate local logic, drastically reducing interconnect capacitance and associated power consumption.
3Speed
If a single large switching device is used, then power can be switched on quickly, but voltage droops occur during operation
Solution Approach 1:
By segmenting the power delivery network into multiple small local switches, each switch handles a minimal capacitive load. This allows each switch to charge and discharge its local interconnect capacitance rapidly without causing significant voltage droops, achieving both fast response time and voltage stability.
4Loss of energy
If local cell-level power switches are implemented, then power consumption is reduced and voltage droops are minimized, but device complexity increases
Solution Approach 1:
The patent merges the power switch with the logic cell structure itself, integrating the power gating function directly into the cell design. This co-integration approach minimizes additional layout area and simplifies the overall device architecture by combining multiple functions within the same structural footprint.
Data Source
AI summary
A power gating switch is described at a local cell level of an integrated circuit die. In one example a plurality of logic cells have a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell. A power switch for each logic cell is coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell.