Local Clearing Control for Translation Lookaside Buffer Entries
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Solution Overview
Problem
Current computing environments face challenges in efficiently managing and clearing Translation Lookaside Buffers (TLBs) across multiple processors, leading to unpredictable results and performance issues due to the lack of effective mechanisms for invalidating and clearing TLB entries, especially when table entries become invalid or change states.
Innovation Solution
The introduction of the Invalidate Dynamic Address Translation (DAT) Table Entry (IDTE) instruction and the Compare and Replace DAT Table Entry (CRDTE) instruction, which allow for selective clearing of TLB entries based on address-space-control elements and table entries, ensuring that TLBs are updated correctly and efficiently, even when entries become invalid or change states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TLB entries are cleared across multiple processors without a standardized mechanism, then memory translation consistency may be maintained, but system performance deteriorates due to unpredictable clearing behavior and repeated invalidation operations
Solution Approach 1:
The IPTE instruction provides a universal mechanism that can invalidate and clear TLB entries across single or multiple processors depending on the configuration. The instruction is designed to work in both uniprocessor and multiprocessor environments, providing consistent behavior regardless of the number of processors involved.
Solution Approach 2:
The system performs preliminary invalidation of the specified page table entry before clearing the TLB. This ensures that when TLB entries are cleared, the corresponding page table entry is already marked as invalid, preventing any potential inconsistency between the TLB state and the page table state.
2Measurement precision
If TLB entries are selectively cleared based on address space control elements, then clearing precision is improved, but device complexity increases due to the need to match and compare control elements
Solution Approach 1:
The IPTE instruction enables selective clearing of TLB entries based on specific address space control elements. By providing parameters for specifying the address space control element and the page table entry, the instruction allows precise targeting of only the relevant TLB entries that need to be cleared, rather than clearing all TLB entries indiscriminately.
3Reliability
If invalidation indicators are set in data structure entries, then invalidation reliability is improved, but loss of time occurs due to the additional steps required to set and check indicators
Solution Approach 1:
The IPTE instruction merges the invalidation of the page table entry and the clearing of the TLB into a single atomic operation. By combining these two operations that were previously separate into one instruction, the system eliminates the need for separate invalidation indicator setting and checking steps, reducing the overall time required while maintaining the reliability benefits of proper invalidation.
Data Source
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AI summary
A computer implemented instruction is executed. One or more translation table entry locations (TLB) are specified by the instruction. Based on a local-clearing (LC) control specified by the instruction being a first value, the processor selectively clears TLBs in a plurality of the CPUs in a configuration of entries corresponding to the determined translation table entry location. Based on the local-clearing (LC) being a second value, the processor selectively clears only the TLBs of the CPU executing the instruction of entries corresponding to the determined translation table entry location. A computer program product, computer system and computer implemented method are provided.