Local DELPHI Thermal Resistance Model for Semiconductor Junction Temperature
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Solution Overview
Problem
Current thermal resistance analysis models for semiconductor integrated circuits lack precision in predicting junction temperatures and thermal resistances, especially for local heat generation scenarios, as they either oversimplify the internal structure or are too complex to be practical.
Innovation Solution
A thermal resistance analysis model that includes a multi-thermal resistance network with specific nodes and resistances between them, such as the Local DELPHI model, which adds a plate node to represent non-local heat-generating portions of the semiconductor chip, providing a more accurate representation of local heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-precision model considering internal structures of semiconductor integrated circuits is used, then measurement precision of junction temperatures is improved, but device complexity increases
Solution Approach 1:
The semiconductor chip is segmented into multiple thermal zones (first thermal zone, second thermal zone, third thermal zone) with different thermal characteristics. Each zone is assigned a specific heat capacity and thermal conductivity, allowing the model to capture local thermal variations without requiring detailed internal structure information for the entire chip. This segmentation approach achieves satisfactory precision for locally heat-generating circuits while keeping the model complexity manageable.
Solution Approach 2:
Different thermal properties (specific heat capacity, thermal conductivity) are assigned to different spatial zones within the semiconductor chip. The first thermal zone has distinct properties from the second and third zones, reflecting the local thermal characteristics of different chip regions. This allows the model to accurately represent local heat generation effects without requiring a uniformly detailed model of the entire chip structure.
2Measurement precision
If computational fluid dynamics (CFD) analysis is applied to analyze thermal interference between adjacent components, then measurement precision is improved, but device complexity and computational requirements increase
Solution Approach 1:
Instead of performing complex CFD simulations, the patent uses a simplified thermal resistance network model that copies the essential thermal behavior of the semiconductor device. The model uses thermal resistances and heat capacities to represent heat flow paths, providing a computationally efficient alternative to CFD that captures the dominant thermal characteristics without requiring detailed fluid dynamics calculations.
3Device complexity
If existing thermal resistance models are used for locally heat-generating circuits, then device complexity is reduced, but measurement precision of junction temperatures deteriorates
Solution Approach 1:
The chip is divided into multiple thermal zones with zone-specific thermal properties, allowing the simple thermal resistance model structure to capture local thermal effects. This segmentation enables the model to handle local heat generation scenarios accurately while maintaining the simplicity of the thermal resistance network approach.
Solution Approach 2:
Different thermal properties are assigned to different zones within the chip to reflect local thermal characteristics. This allows the model to accurately represent local heat generation without requiring a complex overall model structure, achieving satisfactory precision for local thermal analysis.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The Local DELPHI model achieves satisfactory precision in predicting junction temperatures and thermal resistances for locally heat-generating semiconductor integrated circuits, improving upon existing models by accurately modeling local heat generation with reduced computational complexity.
Implementation Method 1
a first thermal resistance between the junction node and the plate node; and a second thermal resistance between the plate node and the bottom inner node
Data Source
AI summary
A thermal resistance analysis model of a semiconductor integrated circuit comprising a die and a semiconductor chip disposed on the die, the die constituting a bottom inner node BI, the semiconductor chip including a local heat-generating portion constituting a junction node JN, the semiconductor chip constituting an additional plate node PN, a first thermal resistance θJP between the junction node JN and the additional plate node PN; and a second thermal resistance θPBI between the additional plate node PN and the bottom inner node BI, wherein the semiconductor integrated circuit is expressed by a multi-thermal resistance network. Disclosed herein are a thermal resistance analysis model with satisfactory precision as a thermal resistance analysis model of locally heat-generating semiconductor integrated circuits; and a semiconductor integrated circuit to which such a thermal resistance analysis model is applied.