Local Driver Power Circuits for Memory Leakage Reduction
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Solution Overview
Problem
Conventional memory devices experience increased leakage currents and longer recovery times during power down and back on modes due to the global power driver's load on GIO drivers, affecting responsiveness and power efficiency.
Innovation Solution
The implementation of a memory device with local driver power circuits, including P-type and N-type MTCMOS, which provide independent multi-threshold power and ground signals to row driver circuits, reducing leakage currents and enhancing mode switching responsiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a global power driver is used to power GIO drivers in all memory banks, then power management is simplified, but leakage currents increase during standby mode
Solution Approach 1:
The patent divides the global power driver into local power drivers for each memory bank. Each local power driver independently controls power supply to GIO drivers in its corresponding memory bank, enabling selective power gating and reducing cumulative leakage currents during standby mode while maintaining simplified power management through modular architecture.
2Loss of energy
If multi-threshold power signals are used to reduce leakage current, then power efficiency improves, but circuit size increases
Solution Approach 1:
The patent implements multi-threshold power signals locally at each memory bank through dedicated local power drivers. Each local driver generates appropriate high-threshold and low-threshold power signals for its corresponding GIO drivers, achieving effective leakage reduction with high threshold voltage devices while maintaining good separation from ground power supply, without requiring global circuit redesign.
3Quantity of substance
If the number of memory cells in memory array increases, then storage capacity improves, but responsiveness during mode switching deteriorates
Solution Approach 1:
The patent segments the power distribution architecture into global and local components. The global power driver maintains active power for large memory arrays, while local power drivers handle rapid mode switching for GIO drivers in each memory bank. This segmentation allows the system to support increased memory cell density while maintaining fast mode switching responsiveness through localized power control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces leakage currents during standby mode and accelerates the recovery time when transitioning from power down to active mode, improving the overall power efficiency and responsiveness of the memory device.
Implementation Method 1
Multi-threshold complementary metal oxide semiconductor (MTCMOS) is known to be an effective power-gating technique to simultaneously reduce IC's leakage power consumption and maintain IC's high performance by effectively use high-threshold voltage and low-threshold voltage devices
Implementation Method 2
an N-type MTCMOS may generate a multi-threshold power signal VMTL from the ground power supply VSS, and the multi-threshold power signal VMTL also features high threshold voltage and good separation from the ground power supply VSS
Data Source
AI summary
Provided is a memory device, including a plurality of memory banks. Each of the memory banks includes a memory array and a driver circuit. The driver circuit is coupled to the memory array, arranged to operably write data to the memory array according to write signals. The driver circuit includes a plurality of row driver circuits each coupled to a row of the memory cells. A global driver power circuit coupled to the row driver circuits in the plurality of memory banks to provide a global driver power. Each of the memory banks further includes a local driver power circuit coupled to respective row driver circuits in each of the memory banks to provide a local driver power. The local driver power circuit includes a first P-type MTCMOS coupled to a supply voltage and a control signal, controlled by the control signal to provide a local multi-threshold power signal to the respective row driver circuits.