Local Interconnect Air-Gap Structure for RF RC Delay Reduction
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Solution Overview
Problem
The increasing RC delay in semiconductor devices, particularly in RF devices, due to parasitic capacitance and wire resistance, hinders signal propagation speed and efficiency.
Innovation Solution
The method involves forming local interconnects with reduced height and introducing air-gaps between the contacts and the back-end metallization layers to reduce parasitic capacitance and resistance, thereby minimizing RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wiring is used to transmit signals, then electrical connectivity is achieved, but RC delay increases due to parasitic capacitance and wire resistance
Solution Approach 1:
The patent extracts the problematic dielectric material surrounding the local interconnects and replaces it with air-gaps. This removes the parasitic capacitance source while maintaining the interconnect's structural integrity and electrical functionality, directly addressing the RC delay issue.
Solution Approach 2:
The patent introduces air-gaps (porous structure) around the local interconnects to reduce parasitic capacitance. The air-gaps create a porous configuration that minimizes dielectric material contact with the interconnect, thereby reducing capacitive coupling and RC delay.
2Reliability
If local interconnects are made taller to connect to back-end metallization, then connectivity is improved, but parasitic capacitance and RC delay increase
Solution Approach 1:
The patent removes dielectric material from around the local interconnects to create air-gaps, extracting the source of parasitic capacitance. This allows taller interconnects to be used for connectivity without proportionally increasing RC delay, as the air-gaps minimize capacitive coupling along the extended height.
Solution Approach 2:
The patent changes the dielectric parameter (permittivity) from high-k dielectric material to air (k≈1) in the regions surrounding the local interconnects. This parameter change dramatically reduces parasitic capacitance while maintaining the interconnect's electrical connectivity function.
3Loss of time
If air-gaps are introduced to reduce parasitic capacitance, then RC delay decreases, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary patterning and etching to define the air-gap regions before forming the local interconnects. By pre-establishing the air-gap structures, the subsequent interconnect formation becomes simpler and more controlled, reducing overall manufacturing complexity despite the added air-gap creation steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces RC delay by optimizing the height of local interconnects and incorporating air-gaps, leading to faster signal propagation and improved device performance.
Implementation Method 1
The increasing RC delay in semiconductor devices, particularly in RF devices, due to parasitic capacitance and wire resistance
Data Source
AI summary
The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.