Local Interconnect Defect Detection in 3D NAND Memory Arrays
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Solution Overview
Problem
Monolithic three-dimensional semiconductor memory devices face challenges in detecting defects, particularly in NAND string structures, where defects such as word line to word line shorts and bit line to low voltage signal shorts can lead to data corruption and operational failures, requiring effective diagnostic methods to identify and isolate these issues.
Innovation Solution
A method involving biasing circuitry and current detection circuitry to perform built-in self-test (BIST) operations, including reference current level determination and leakage current level determination, to identify defects by comparing current levels drawn by global interconnect lines under different voltage conditions, thereby determining whether a selected block has associated defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If built-in self-test operations are implemented to detect defects in monolithic three-dimensional semiconductor memory devices, then defect detection capability is improved, but device complexity increases due to additional biasing circuitry and current detection circuitry
Solution Approach 1:
The biasing circuitry and current detection circuitry are designed to serve multiple functions: they enable both normal memory operations and defect detection operations using the same hardware infrastructure. The global interconnect lines serve both as data pathways during normal operation and as test pathways during BIST operations, reducing the need for separate dedicated test hardware and thereby limiting the increase in device complexity.
2Measurement precision
If reference current level determination and leakage current level determination are performed to identify defects, then measurement precision is improved, but use of energy increases due to multiple voltage applications
Solution Approach 1:
The BIST operation applies high voltage selectively and temporarily only to the extent necessary to detect defects, rather than maintaining continuous high voltage. The reference current determination and leakage current determination are performed as discrete, controlled measurements that use high voltage only when needed for comparison, thereby achieving precise defect detection while limiting overall energy consumption during the testing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient detection of defects within the memory device, reducing the risk of data corruption and operational failures by identifying and isolating faulty blocks, thereby improving the reliability and performance of the memory system.
Implementation Method 1
determining the reference current level from an amount of current drawn by the global interconnect lines with the array biased in this way
Data Source
AI summary
Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.