Local Interconnect Routing at M0 to Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor integrated circuits scale down, the increasing complexity and density of devices lead to challenges in reducing parasitic capacitances in interconnect structures, which affect device performance by causing signal integrity issues.
Innovation Solution
The implementation of a local interconnect structure that routes connections directly to the gate, drain, and source terminals of transistor devices, such as finFETs, using metals like copper, ruthenium, or cobalt, to minimize interconnect length and reduce parasitic capacitances at the M0 interconnect level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnect length is reduced to minimize parasitic capacitance, then device performance is improved, but routing complexity increases
Solution Approach 1:
The patent divides the interconnect routing into two distinct segments: global interconnect lines for long-distance connections and local interconnect lines for short-distance connections to transistor terminals. This segmentation allows each type of interconnect to be optimized independently, with local interconnects routed directly to gate, drain, and source terminals to minimize parasitic capacitance and improve signal integrity.
Solution Approach 2:
The patent applies different routing strategies to different parts of the interconnect structure. Local interconnect lines are routed with specific attention to minimizing length and parasitic effects near transistor terminals, while global interconnect lines handle longer-distance connections. This local optimization of routing quality addresses signal integrity issues without requiring complete redesign of the entire interconnect system.
2Reliability
If local interconnect structure is routed at same level as reference metal line, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes the same interconnect level (M0) for both reference metal lines and local interconnect structures, effectively using the planar dimension efficiently. By routing local interconnects at the same level as reference metal lines rather than requiring additional vertical layers, the patent reduces parasitic capacitance while managing manufacturing precision through established fabrication processes for multi-pattern routing at the same metal level.
Data Source
AI summary
The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.