Local Interconnect Material Split for Logic and Memory Areas
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Solution Overview
Problem
The material used to form local interconnects underneath memory devices can negatively impact the overall performance of the memory device, while the same material may be favorable for the logic area.
Innovation Solution
Form local interconnects in the logic and memory areas using different metals or metal alloys that maximize overall performance for a given application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same metal material is used for local interconnects in both logic and memory areas, then manufacturing simplicity is maintained, but memory device performance is degraded
Solution Approach 1:
The patent applies local quality by using different metal materials for local interconnects in different functional areas. Specifically, copper is used in logic areas while tungsten is used in memory areas, allowing each region to have material properties optimized for its specific functional requirements rather than using a uniform material throughout the device
2Reliability
If different metal materials are used for local interconnects in logic and memory areas, then overall device performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnect structure by functional area, dividing the device into logic areas and memory areas with distinct material compositions. This segmentation allows independent optimization of materials for each functional block while maintaining overall device performance
Solution Approach 2:
The patent introduces an intermediary approach by using a common dielectric material (e.g., spin-on-glass) and standardized fabrication processes that accommodate multiple metal materials. This intermediary framework simplifies the integration of different materials by providing a unified processing environment
Data Source
AI summary
A semiconductor device and formation thereof. The semiconductor device including: a first bottom interconnect formed within a first dielectric layer and located within a logic area of the semiconductor device; a second bottom interconnect formed within the first dielectric layer and located within a memory area of the semiconductor device; and a memory device formed on top of the second bottom interconnect located within the memory area of the semiconductor device, wherein: a first metal material used to form the first bottom interconnect located in the logic area is different than a second metal material used to form the second bottom interconnect located in the memory area.