Local Interconnect Structure Without Overlying Metal Routing
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Solution Overview
Problem
Existing interconnect fabrication methods in semiconductor ICs face challenges with increasing resistance and capacitance due to dimensional scaling, leading to RC-delay issues, and the addition of metal layers increases cost and degrades device performance.
Innovation Solution
A local interconnect fabrication process that routes interconnects through a VIA layer instead of overlying metal layers, reducing the number of metal layers and improving routing efficiency, thereby reducing costs and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional metal layers are added to the multi-level interconnect network, then resistance is reduced by increasing interconnect dimensions, but device performance degrades due to increased total interconnect length and manufacturing cost increases
Solution Approach 1:
The patent introduces a via-less interconnect structure that routes signals horizontally through the interlayer dielectric layer rather than vertically through additional metal layers. This dimensional change allows signal transmission in the planar direction (along the substrate surface) instead of requiring stack-up of multiple metal layers, thereby reducing the number of metal layers while maintaining interconnect functionality
Solution Approach 2:
The patent extracts the via structure from the traditional interconnect architecture. By removing the via component that connects metal layers vertically, the design eliminates the need for additional metal layers to achieve signal routing, thus reducing overall interconnect complexity and the number of fabrication steps required
2Ease of manufacture
If dimensional scaling is applied to improve production efficiency and lower costs, then manufacturing cost decreases, but resistance increases and capacitance increases leading to RC-delay degradation
Solution Approach 1:
The via-less interconnect structure enables longer horizontal routing paths within the interlayer dielectric layer without requiring proportional increases in vertical stacking. This allows maintaining larger effective conductor dimensions for lower resistance while keeping the overall device footprint scaled down, thus improving RC-delay performance without sacrificing manufacturing efficiency
Solution Approach 2:
The patent provides a flexible interconnect architecture where the horizontal routing length in the interlayer dielectric can be dynamically adjusted based on specific circuit requirements. This dynamic design freedom allows optimization of conductor dimensions and routing paths to balance resistance, capacitance, and manufacturing constraints for each specific application
Data Source
AI summary
A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.