Local Interconnect Misalignment Tolerance in Semiconductor Memory
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Solution Overview
Problem
Conventional methodologies for reducing design features in non-volatile memory devices face challenges in meeting data retention requirements and manufacturing throughput, particularly in SONOS-type EEPROM devices where the reduction of design features complicates charge storage and interconnect formation.
Innovation Solution
A method for forming a semiconductor memory device involves creating a pair of source select transistors on a substrate, forming a source region between them, and using a mask layer to define a local interconnect area with a metal contact, where the interconnect width is narrower than the distance between the transistors, allowing for efficient charge storage and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design features are reduced to increase density, then device density is improved, but manufacturing precision deteriorates
Solution Approach 1:
The interconnect structure is segmented into multiple functional regions: a wider first portion for robust alignment and connection to the source region, and a narrower second portion for achieving high density. This segmentation allows each portion to optimize for its specific function, resolving the contradiction between density and manufacturing precision.
Solution Approach 2:
Different portions of the interconnect are given different widths tailored to their specific functions. The first portion has a wider width to accommodate alignment tolerances and ensure reliable connection, while the second portion has a narrower width to achieve high device density. This local differentiation resolves the contradiction by applying appropriate dimensions in appropriate locations.
2Quantity of substance
If design features are reduced to increase density, then device density is improved, but reliability deteriorates
Solution Approach 1:
The interconnect is segmented with a wider first portion that provides enhanced connection reliability to the source region, while the narrower second portion achieves high density. The wider first portion acts as a robust connection interface that maintains signal integrity and reduces variability, thereby preserving reliability despite overall feature reduction.
Solution Approach 2:
The interconnect structure implements local quality by providing a wider first portion specifically at the connection point to the source region, where reliability is most critical. This wider section compensates for alignment variations and ensures robust electrical connection, while the narrower second portion achieves high density in regions where connection reliability is less critical.
3Ease of manufacture
If conventional interconnect width is used, then manufacturing ease is improved, but device density deteriorates
Solution Approach 1:
The interconnect is divided into two portions with different widths. The first portion has a wider width that is easier to manufacture with standard alignment tolerances, while the second portion has a narrower width that achieves high density. This segmentation allows the manufacturing process to handle the easier-to-form wider portion while achieving the density benefits of narrower features overall.
Solution Approach 2:
Different sections of the interconnect are given different widths appropriate to their function and manufacturing constraints. The first portion uses a wider width that is more tolerant to manufacturing variations, making it easier to manufacture reliably. The second portion uses a narrower width to achieve high device density in the active area, resolving the contradiction between ease of manufacture and device density.
Data Source
AI summary
A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.