Local Interconnect Structure for Semiconductor Contacts
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Solution Overview
Problem
As semiconductor device dimensions shrink, accurately and repeatedly manufacturing integrated circuits that meet performance criteria becomes challenging due to increased risks of short circuits caused by reduced lateral spacing between transistor features, making it difficult to form reliable conductive contacts without increasing spacing between transistors, which would be costly and counterproductive to the trend of reducing product size.
Innovation Solution
The method involves forming dual level source/drain contacts with a local interconnect structure that spans isolation regions, using a patterned mask layer to expose and etch a recess above the interconnect structure, and filling it with insulating material, while also forming gate contacts positioned above the insulating material in the recess to prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lateral spacing between transistor features is reduced to continue miniaturization, then device density and productivity are improved, but the risk of short circuits increases and manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The patent segments the continuous local interconnect structure into isolated portions by forming recesses and filling them with insulating material. This segmentation prevents electrical shorts between adjacent transistors while maintaining the miniaturized layout, effectively resolving the contradiction between high device density and short circuit risk
Solution Approach 2:
The patent applies local quality by creating spatially varying structures: the local interconnect structure is present in some regions (above isolation regions) and absent in others (above active regions), with insulating material selectively placed in recesses. This localized differentiation enables precise control of electrical connectivity to prevent shorts while maintaining miniaturization
2Reliability
If lateral spacing between transistor features is increased to reduce short circuit risk, then manufacturing precision and reliability are improved, but device density and productivity deteriorate
Solution Approach 1:
The patent transitions from two-dimensional spacing solutions to three-dimensional structures by forming vertical recesses and filling them with insulating material. This dimensional change enables reliable short circuit prevention without increasing lateral spacing, thereby maintaining high device density while improving reliability
3Ease of manufacture
If a continuous local interconnect structure is formed to span isolation regions, then ease of manufacture is improved, but the risk of electrical shorts between adjacent active regions increases
Solution Approach 1:
The patent applies preliminary action by forming recesses in the local interconnect structure before completing the interconnect formation process. This preliminary modification creates isolated segments that prevent shorts while maintaining the overall ease of manufacture through a systematic, pre-planned process approach
Solution Approach 2:
The insulating material acts as an intermediary element that is introduced into the recesses of the local interconnect structure. This intermediary prevents direct electrical contact between adjacent active regions while allowing the interconnect structure to maintain its continuous appearance and manufacturing simplicity
Data Source
AI summary
One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.