Local Interconnect VIA Structure for Lower RC Delay
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in interconnect performance degradation due to increased resistance and capacitance with dimensional scaling, leading to RC-delay issues, and the addition of metal layers increases cost and complexity.
Innovation Solution
A local interconnect fabrication process that routes interconnects through a VIA layer instead of overlying metal layers, reducing the number of metal layers and improving routing efficiency, thereby decreasing interconnect length and cost while enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional metal layers are added to the multi-level interconnect network, then resistance is reduced by increasing interconnect dimensions and routing paths, but total interconnect length increases and manufacturing cost increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive plugs through dielectric layers to create three-dimensional interconnect structures. This allows routing signals vertically through different layers rather than only horizontally, reducing the need for additional metal layers and decreasing total interconnect length while maintaining performance
Solution Approach 2:
The interconnect structure is segmented into multiple functional components including conductive plugs, metal traces, and via structures distributed across different dielectric layers. This segmentation allows optimization of each segment's function, reducing overall interconnect length and improving routing efficiency without requiring a uniform increase in metal layer count
2Reliability
If additional metal layers are added to the multi-level interconnect network, then resistance is reduced by increasing interconnect dimensions and routing paths, but manufacturing cost increases due to additional photomasks and design time
Solution Approach 1:
The patent employs universal processing steps and materials that can be applied across different interconnect configurations. The same dielectric materials, conductive plug formation processes, and metal deposition techniques are used regardless of the specific routing requirements, reducing the need for additional photomasks and specialized manufacturing steps
Solution Approach 2:
By utilizing vertical routing through conductive plugs and via structures, the patent reduces the need for additional horizontal metal layers. This dimensional approach decreases the number of photomasks required and simplifies the manufacturing process while maintaining interconnect performance
3Productivity
If dimensional scaling is applied to improve production efficiency and lower costs, then minimum feature size decreases, but resistance increases and RC-delay increases
Solution Approach 1:
The patent employs composite interconnect structures combining different materials with complementary properties. Low-k dielectric materials are used to reduce capacitance, while copper or other low-resistance metals are used for conductive paths. This material composition allows dimensional scaling while maintaining acceptable RC-delay characteristics
Solution Approach 2:
The patent compensates for increased resistance in scaled dimensions by utilizing vertical routing through conductive plugs and multiple dielectric layers. This three-dimensional approach provides additional routing paths that can be optimized to reduce total interconnect length and mitigate RC-delay effects
Data Source
AI summary
A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.