Local Interconnects for Replacement Gate Structures
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Solution Overview
Problem
The challenge in semiconductor technology is forming reliable contact structures for source and drain regions and gate electrodes without electrical shorting, especially in replacement gate integration schemes, due to lithographic misalignment and pattern distortion.
Innovation Solution
A method involving the formation of a gate-level structure with a planarized dielectric layer, followed by deposition of a contact-level dielectric layer, where substrate and gate contact via holes are created to be filled with a conductive material, forming substrate and gate contact structures that provide electrical connections between laterally spaced components on the semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequentially forming different groups of contact structures is used in replacement gate integration schemes, then contact structures can be formed to source and drain regions and gate electrodes, but electrical shorts among components occur due to lithographic misalignment during multiple lithographic exposure steps
Solution Approach 1:
The contact formation process is segmented into distinct stages: first forming substrate contact structures through the planarized dielectric layer, then forming gate contact structures through the contact-level dielectric layer. This segmentation allows each contact type to be formed with optimized lithographic parameters, reducing misalignment risks between different contact groups while maintaining electrical connection reliability
Solution Approach 2:
The planarized dielectric layer is formed as a preliminary structure before contact formation, providing a flat, stable base that enables precise lithographic patterning of substrate contacts. This preliminary action establishes a reference plane that improves alignment precision for subsequent contact formation steps
2Ease of manufacture
If sequentially forming different groups of contact structures is used in replacement gate integration schemes, then contact structures can be formed to source and drain regions and gate electrodes, but pattern distortion occurs due to resist shadowing
Solution Approach 1:
The dielectric layer structure is designed with different local properties: the planarized dielectric layer provides a flat surface for substrate contact patterning, while the contact-level dielectric layer provides insulation and structural support for gate contacts. This local differentiation allows each region to be optimized for its specific function, preventing pattern distortion while enabling complete contact structure formation
Solution Approach 2:
The invention introduces a vertical dimension by creating a multi-layer dielectric structure with distinct planarized and contact-level layers. This dimensional approach separates the patterning planes for substrate and gate contacts, allowing independent optimization of lithographic parameters for each contact type without mutual interference, thus maintaining pattern fidelity
3Reliability
If replacement gate structures including high-k dielectric material gate dielectric and metallic gate electrode are used, then device performance is improved, but the complexity of forming reliable contact structures without electrical shorting increases
Solution Approach 1:
The contact formation process is divided into sequential stages with distinct dielectric layers: substrate contacts are formed through the planarized dielectric layer, while gate contacts are formed through the contact-level dielectric layer. This segmentation simplifies the overall process by treating different contact types as separate, manageable steps rather than a single complex operation, reducing formation complexity while maintaining device performance
Solution Approach 2:
The planarized dielectric layer serves as an intermediary structure between the substrate and the contact-level dielectric layer. It provides a stable, flat foundation that simplifies subsequent contact formation steps, acting as a mediator that reduces the complexity of forming reliable contacts to high-k gate structures by establishing a controlled intermediate platform
Data Source
AI summary
After forming replacement gate structures that are embedded in a planarized dielectric layer on a semiconductor substrate, a contact-level dielectric layer is deposited over a planar surface of the planarized dielectric layer and the replacement gate structures. Substrate contact via holes are formed through the contact-level dielectric layer and the planarized dielectric layer, and metal semiconductor alloy portions are formed on exposed semiconductor materials. Gate contact via holes are subsequently formed through the contact-level dielectric layer. The substrate contact via holes and the gate contact via holes are simultaneously filled with a conductive material to form substrate contact structures and gate contact structures. The substrate contact structures and gate contact structures can be employed to provide local interconnect structures that provide electrical connections between two components that are laterally spaced on the semiconductor substrate.