Local I/O Line Precharging for Semiconductor Memory Devices
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in performing precharging operations on local input/output lines under both short and long tRCD conditions, leading to unsatisfactory operation quality, bit line disturbance, and degradation in low-voltage high-speed operations.
Innovation Solution
A read data path circuit that employs NMOS charging under short tRCD conditions and PMOS precharging under long tRCD conditions, using a local input/output line precharging unit with NMOS and PMOS transistors to precharge and equalize local input/output lines, minimizing bit line disturbance and enabling high-speed, low-voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single precharging circuit is used for local input/output lines, then the circuit structure is simple, but the operation quality is unsatisfactory under both short and long tRCD conditions
Solution Approach 1:
The precharging circuit is divided into two separate circuits: a first precharging circuit for short tRCD conditions and a second precharging circuit for long tRCD conditions. Each circuit is optimized for its specific operating condition, resolving the contradiction between circuit simplicity and operational reliability across varying tRCD conditions.
Solution Approach 2:
The patent implements dynamic switching between different precharging circuits based on the tRCD condition. A control circuit determines whether the first or second precharging circuit should be activated, allowing the system to adapt its precharging behavior to match the current operating conditions, thereby maintaining high operation quality regardless of tRCD duration.
2Speed
If precharging voltage is varied to maximize sensing speed, then sensing performance improves, but noise increases causing voltage level changes
Solution Approach 1:
The patent applies different precharging voltage strategies locally based on the specific tRCD condition. For short tRCD conditions, one precharging voltage profile is used, while for long tRCD conditions, a different profile is applied. This localized optimization allows each circuit to achieve maximum sensing speed appropriate for its operating condition without introducing excessive noise.
3Manufacturing precision
If precharging is performed aggressively to reduce bit line disturbance, then sensing accuracy improves, but low-voltage high-speed operation quality degrades
Solution Approach 1:
The patent dynamically adjusts the precharging strategy based on tRCD conditions. The first precharging circuit is optimized for aggressive precharging to reduce bit line disturbance under short tRCD conditions, while the second precharging circuit is optimized for low-voltage high-speed operation under long tRCD conditions. This dynamic adaptation resolves the contradiction between sensing accuracy and operational performance.
Data Source
AI summary
A semiconductor memory device capable of preventing or minimizing bit line disturbance and performing a low-voltage high-speed operation includes a read data path circuit including a bit line sense amplifier, a local input/output line sense amplifier, a column selecting unit to operationally connect bit lines connected to the bit line sense amplifier to local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal, and a local input/output line precharging unit to precharge the pair of local input/output lines by a first precharging unit, equalizing the pair of local input/output lines by an equalizing unit, and to precharge the local input/output lines by a second precharging unit following an elapsed time after the bit line sense amplifier is activated, while the column selection is deactivated.