Local Memory Translation Table for Virtualized GPU
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Solution Overview
Problem
Current graphics processing units (GPUs) face challenges in efficiently processing graphics data and machine-learning operations due to limitations in parallel processing capabilities and resource allocation, particularly in virtualized environments where multiple operating systems share a single physical PCI Express bus.
Innovation Solution
The implementation of a graphics processing unit (GPU) architecture that utilizes a general-purpose graphics processing unit (GPGPU) connected via high-speed interconnects like PCIe or NVLink, with a parallel processing unit that includes a scheduler and processing clusters to efficiently distribute workloads across multiple processing cores, enabling parallel graphics and machine-learning operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single physical PCI Express bus is shared among multiple virtual machines using SR-IOV, then resource utilization is improved, but processing efficiency and parallel processing capabilities deteriorate
Solution Approach 1:
The patent segments the address translation functionality by implementing separate translation tables (first and second translation tables) for different virtual machines, allowing each VM to have its own isolated translation context. This segmentation enables efficient parallel address translations for multiple VMs without interference, resolving the contradiction between shared resource utilization and processing efficiency.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing simultaneous address translation operations across multiple translation tables. Instead of sequential processing, the system performs parallel address translations for different virtual machines at the same time, effectively adding a temporal dimension to resource utilization that maintains both high sharing efficiency and processing speed.
2Adaptability or versatility
If multiple operating systems share a single physical PCI Express bus, then hardware resource sharing is improved, but parallel processing capabilities for graphics and machine-learning operations deteriorate
Solution Approach 1:
The patent introduces translation tables as intermediary structures between the physical PCI Express bus and multiple virtual machines. These translation tables act as mediators that translate virtual addresses to physical addresses, enabling multiple OSes to share the physical bus while maintaining independent parallel processing capabilities through address space isolation.
Solution Approach 2:
The translation table system provides universal functionality that serves multiple virtual machines simultaneously. The same physical PCI Express bus and translation mechanism serve diverse workloads including graphics operations and machine-learning tasks across different VMs, maintaining parallel processing capabilities through unified address translation management.
Data Source
AI summary
Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table.