Local Oscillator Re-Clocking With Programmable Delay Alignment
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Solution Overview
Problem
Conventional frequency divider circuits face challenges in achieving low phase noise and low power consumption over a wide tuning range, leading to increased design complexity and potential metastability issues during re-clocking due to misalignment of signal edges.
Innovation Solution
A local oscillator signal generation circuit incorporating a Programmable Delay Cell (PDL) and a control arrangement that generates overlapping pulse windows to align the data signal edges with the reference clock signal, using logic gates and a state machine to adjust the delay and ensure stable re-clocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional VCO is used for frequency tuning, then frequency tuning capability is achieved, but phase noise performance deteriorates over wide tuning ranges
Solution Approach 1:
The system segments the frequency tuning function into two parts: a VCO that operates over a limited frequency range with optimal phase noise performance, and a programmable frequency divider that handles the extension of the overall tuning range. This segmentation allows the VCO to maintain good phase noise while the divider extends the usable frequency range.
Solution Approach 2:
A programmable frequency divider is introduced as an intermediary component between the VCO and the mixer. This divider acts as a mediator that extends the tuning range without degrading the phase noise performance of the VCO, effectively decoupling the tuning range extension from phase noise degradation.
2Adaptability or versatility
If a programmable frequency divider is added to extend tuning range, then tuning range is improved, but device complexity increases
Solution Approach 1:
The frequency divider is designed to perform multiple functions: it extends the tuning range, provides re-clocking to reduce jitter, and generates balanced I and Q outputs with balanced duty cycles. By consolidating these functions into a single component, the overall device complexity is reduced compared to using separate circuits for each function.
3Measurement precision
If re-clocking is used to reduce jitter, then phase noise is improved, but metastability issues occur due to signal misalignment
Solution Approach 1:
The system performs preliminary alignment of the data signal edges with the reference clock signal edges before the re-clocking operation. By ensuring proper timing alignment in advance, the system prevents metastability conditions from occurring during the re-clocking process, thereby maintaining both low phase noise and high reliability.
Solution Approach 2:
The system uses feedback mechanisms to monitor and adjust the timing relationship between the data signal and the reference clock signal. This feedback ensures that the signals remain properly aligned, preventing metastability while maintaining the jitter reduction benefits of re-clocking.
Data Source
AI summary
A local oscillator signal generation circuit for a frequency divider circuit is disclosed. The local oscillator signal generation circuit includes a delay device adapted to delay a data signal according to a control signal, a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided to its clock input terminal and a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and to generate a control signal based on the first and second partially overlapping pulse windows and the reference clocking signal. The control signal is provided to the delay device to control the amount by which the data signal is delayed so that the data signal is stable when it is sampled by the data flip-flop. A local oscillator signal is derived from the output of the data flip-flop.