Local Parity Caching for Memory Error Correction Overhead
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Solution Overview
Problem
Existing error detection and correction schemes for data stored in off-chip memory require frequent updates and recalculations of parity blocks, leading to inefficiencies and performance delays due to the need to write revised parity blocks back to memory during data modifications.
Innovation Solution
Implementing a local parity storage scheme where parity information is stored on-chip, allowing for efficient detection and correction of errors by using checksums and cyclic redundancy checks, and reducing the need for off-chip updates by grouping data blocks into sets with a single associated parity block, which is stored and updated locally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity blocks are stored in off-chip memory and updated frequently during data modifications, then error detection and correction capability is maintained, but processing efficiency deteriorates due to write overhead and performance delays
Solution Approach 1:
The patent divides the parity storage function into two segments: frequently accessed parity blocks are cached in on-chip memory (fast access) while less frequently accessed parity blocks remain in off-chip memory (large capacity). This segmentation allows the system to maintain error correction capability while avoiding frequent off-chip writes for hot data, thus resolving the contradiction between reliability and processing efficiency.
Solution Approach 2:
The patent pre-loads parity blocks into on-chip cache memory before they are needed for error correction. By anticipating which parity blocks will be needed and loading them in advance, the system ensures that error detection and correction can proceed using on-chip resources without incurring off-chip write delays, thereby maintaining both reliability and productivity.
2Productivity
If parity information is stored on-chip to reduce write overhead, then processing efficiency is improved, but on-chip storage requirements increase
Solution Approach 1:
The patent applies local quality by storing different types of data in different locations based on their access patterns and size requirements. Hot parity blocks that need frequent access are stored in on-chip cache (high speed, limited capacity), while cold parity blocks are stored in off-chip memory (large capacity, slower access). This localized quality optimization resolves the contradiction between processing efficiency and storage requirements.
Solution Approach 2:
The patent implements a dynamic parity caching strategy where the allocation of on-chip storage resources is not fixed but adapts based on access patterns. Frequently accessed parity blocks are automatically retained in on-chip memory, while less accessed blocks are evicted to off-chip storage. This dynamic approach allows the system to maximize processing efficiency while minimizing on-chip storage usage at any given time.
Data Source
AI summary
A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.