Local Power Block Isolation for Leakage in Multi-Activity Circuits

The patent divides the circuit into multiple activity groups (first activity group, second activity group, etc.) and applies separate power blocking mechanisms to each group. Instead of a single global header/footer controlling the entire circuit, individual power blocking is implemented for each activity group, allowing independent control and reducing the complexity of any single control structure.

The patent implements local power blocking by placing power blocking devices (such as transmission gates or switches) directly at the power supply nodes of specific activity groups that require leakage reduction. This localized approach allows precise control over which portions of the circuit have their leakage blocked, avoiding the need for complex global routing structures while maintaining effective leakage control where needed.

By segmenting the circuit into activity groups and applying power blocking locally to each group rather than globally, the patent reduces the total area required for power blocking structures. Each local power blocking device only needs to handle the current for its specific activity group, allowing for more compact implementation compared to a single global structure that would need to handle the entire circuit current.

The patent merges the power blocking function with existing circuit structures by utilizing available transistors and power supply nodes within each activity group. Rather than adding completely separate global header/footer structures, the power blocking is integrated into the local circuit architecture, reducing additional area requirements.

The patent implements dynamic control of power blocking by using activity detection mechanisms that monitor the operational state of each activity group. When an activity group is detected to be active, the power blocking is automatically removed or reduced, allowing full performance. When inactive, the power blocking is engaged to reduce leakage. This dynamic adjustment ensures that performance is maintained during active operation while achieving leakage reduction during idle periods.

By dividing the circuit into separate activity groups with independent power control, the patent allows different leakage control strategies to be applied to different portions of the circuit simultaneously. High-activity groups can maintain full power connection for optimal performance, while low-activity or idle groups can have aggressive power blocking applied, achieving overall leakage reduction without compromising the performance of critical high-performance circuitry.

The patent applies the same power blocking mechanism to multiple activity groups throughout the circuit, effectively copying the leakage control solution across different portions of the design. This standardized approach allows consistent leakage management across the entire high-density circuit without requiring different solutions for each component, making the technique scalable to high-density designs.

The dynamic activity detection and control mechanism allows the circuit to adapt its power consumption characteristics based on actual usage patterns. In high-density circuits where many transistors are packed closely together, the dynamic control ensures that only actively used portions consume significant power, while idle portions are aggressively power-blocked, counteracting the increased leakage that naturally occurs with smaller feature sizes and higher density.