Local Reinforcement Decoding for Low-Power Memory Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in efficiently decoding data with error correction codes, particularly in portable devices where power consumption and gate counts are critical, due to the limitations of current decoders in correcting errors within a bipartite graph.
Innovation Solution
A system employing a first decoder with lower precision for initial decoding and a second decoder with higher precision to decode over a small subgraph, using a parity check matrix to extract and correct errors, thereby reducing power consumption and gate counts while improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-precision decoder is used to correct errors in memory systems, then error correction capability is improved, but power consumption and gate counts increase
Solution Approach 1:
The decoder is segmented into two distinct decoders with different precision levels. The first decoder handles initial error correction with lower power consumption, while the second decoder provides higher precision correction only when needed. This segmentation allows the system to achieve high error correction capability while minimizing overall power consumption by avoiding continuous use of high-precision decoding resources.
Solution Approach 2:
The system dynamically switches between different decoding precision levels based on the actual error conditions detected in the data. When errors are detected, the system activates the higher-precision second decoder; when no errors are present, it relies on the lower-precision first decoder. This dynamic adaptation optimizes the balance between error correction capability and power consumption in real-time.
2Reliability
If a high-precision decoder is used to correct errors in memory systems, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The decoding function is segmented into two separate decoder units with different complexity levels. The first decoder has lower gate counts and handles routine decoding operations, while the second decoder with higher gate counts is dedicated to complex error correction scenarios. This segmentation allows the system to achieve high error correction capability only when necessary, rather than maintaining high complexity continuously.
Solution Approach 2:
The system applies high-precision decoding (excessive action) only partially - specifically when errors are detected in the data. For error-free data, the simpler first decoder suffices. This partial application of high-precision decoding reduces the average device complexity and gate count requirements while maintaining the capability to correct errors when they occur.
3Ease of operation
If conventional decoders are used for data decoding, then decoding simplicity is maintained, but error correction performance deteriorates
Solution Approach 1:
The decoding process is segmented into two stages: a first simple decoding stage using the first decoder, and a second enhanced decoding stage using the second decoder. This segmentation maintains decoding simplicity for the majority of cases (when errors are absent) while providing enhanced error correction performance when needed. The system structure preserves operational simplicity through clear stage separation.
Solution Approach 2:
The first decoder performs preliminary error correction before the data is passed to the second decoder. This preliminary action handles the common case of no errors or minor errors, maintaining simplicity for routine operations. Only when the preliminary decoding fails to correct all errors does the system proceed to the more complex second decoding stage, thus preserving simplicity while improving overall performance.
Data Source
AI summary
Embodiments of the present disclosure provide a scheme for decoding over a small subgraph which highly likely includes some errors. A controller is configured to: control the first decoder to decode the data, read from the memory device, using a parity check matrix for the error correction code; extract one or more subgraphs from the entire bipartite graph of the parity check matrix, which is defined by a plurality of variable nodes and a plurality of check nodes when a particular condition satisfied; and control the second decoder to decode the decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraphs.